blob: 32af53ef5696b61eb5d5c5d8c551dd0b065a8f32 [file] [log] [blame]
Nikolai Artemievadbae0e2020-10-06 16:59:51 +11001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2014 Google LLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * s25f.c - Helper functions for Spansion S25FL and S25FS SPI flash chips.
19 * Uses 24 bit addressing for the FS chips and 32 bit addressing for the FL
20 * chips (which is required by the overlayed sector size devices).
21 * TODO: Implement fancy hybrid sector architecture helpers.
22 */
23
24#include <string.h>
25
26#include "chipdrivers.h"
27#include "spi.h"
28#include "writeprotect.h"
29
30/*
31 * RDAR and WRAR are supported on chips which have more than one set of status
32 * and control registers and take an address of the register to read/write.
33 * WRR, RDSR2, and RDCR are used on chips with a more limited set of control/
34 * status registers.
35 *
36 * WRR is somewhat peculiar. It shares the same opcode as JEDEC_WRSR, and if
37 * given one data byte (following the opcode) it acts the same way. If it's
38 * given two data bytes, the first data byte overwrites status register 1
39 * and the second data byte overwrites config register 1.
40 */
41#define CMD_WRR 0x01
42#define CMD_WRDI 0x04
43#define CMD_RDSR2 0x07 /* note: read SR1 with JEDEC RDSR opcode */
44#define CMD_RDCR 0x35
45#define CMD_RDAR 0x65
46#define CMD_WRAR 0x71
47
48/* TODO: For now, commands which use an address assume 24-bit addressing */
49#define CMD_WRR_LEN 3
50#define CMD_WRDI_LEN 1
51#define CMD_RDAR_LEN 4
52#define CMD_WRAR_LEN 5
53
54#define CMD_RSTEN 0x66
55#define CMD_RST 0x99
56
57#define CR1NV_ADDR 0x000002
58#define CR1_BPNV_O (1 << 3)
59#define CR1_TBPROT_O (1 << 5)
60#define CR3NV_ADDR 0x000004
61#define CR3NV_20H_NV (1 << 3)
62
63/* See "Embedded Algorithm Performance Tables for additional timing specs. */
64#define T_W 145 * 1000 /* NV register write time (145ms) */
65#define T_RPH 35 /* Reset pulse hold time (35us) */
66#define S25FS_T_SE 145 * 1000 /* Sector Erase Time (145ms) */
67#define S25FL_T_SE 130 * 1000 /* Sector Erase Time (130ms) */
68
69static int s25f_legacy_software_reset(const struct flashctx *flash)
70{
71 struct spi_command cmds[] = {
72 {
73 .writecnt = 1,
74 .writearr = (const uint8_t[]){ CMD_RSTEN },
75 .readcnt = 0,
76 .readarr = NULL,
77 }, {
78 .writecnt = 1,
79 .writearr = (const uint8_t[]){ 0xf0 },
80 .readcnt = 0,
81 .readarr = NULL,
82 }, {
83 .writecnt = 0,
84 .writearr = NULL,
85 .readcnt = 0,
86 .readarr = NULL,
87 }};
88
89 int result = spi_send_multicommand(flash, cmds);
90 if (result) {
91 msg_cerr("%s failed during command execution\n", __func__);
92 return result;
93 }
94
95 /* Allow time for reset command to execute. The datasheet specifies
96 * Trph = 35us, double that to be safe. */
97 programmer_delay(T_RPH * 2);
98
99 return 0;
100}
101
102/* "Legacy software reset" is disabled by default on S25FS, use this instead. */
103static int s25fs_software_reset(struct flashctx *flash)
104{
105 struct spi_command cmds[] = {
106 {
107 .writecnt = 1,
108 .writearr = (const uint8_t[]){ CMD_RSTEN },
109 .readcnt = 0,
110 .readarr = NULL,
111 }, {
112 .writecnt = 1,
113 .writearr = (const uint8_t[]){ CMD_RST },
114 .readcnt = 0,
115 .readarr = NULL,
116 }, {
117 .writecnt = 0,
118 .writearr = NULL,
119 .readcnt = 0,
120 .readarr = NULL,
121 }};
122
123 int result = spi_send_multicommand(flash, cmds);
124 if (result) {
125 msg_cerr("%s failed during command execution\n", __func__);
126 return result;
127 }
128
129 /* Allow time for reset command to execute. Double tRPH to be safe. */
130 programmer_delay(T_RPH * 2);
131
132 return 0;
133}
134
135static int s25f_poll_status(const struct flashctx *flash)
136{
137 uint8_t tmp = spi_read_status_register(flash);
138
139 while (tmp & SPI_SR_WIP) {
140 /*
141 * The WIP bit on S25F chips remains set to 1 if erase or
142 * programming errors occur, so we must check for those
143 * errors here. If an error is encountered, do a software
144 * reset to clear WIP and other volatile bits, otherwise
145 * the chip will be unresponsive to further commands.
146 */
147 if (tmp & SPI_SR_ERA_ERR) {
148 msg_cerr("Erase error occurred\n");
149 s25f_legacy_software_reset(flash);
150 return -1;
151 }
152
153 if (tmp & (1 << 6)) {
154 msg_cerr("Programming error occurred\n");
155 s25f_legacy_software_reset(flash);
156 return -1;
157 }
158
159 programmer_delay(1000 * 10);
160 tmp = spi_read_status_register(flash);
161 }
162
163 return 0;
164}
165
166/* "Read Any Register" instruction only supported on S25FS */
167static int s25fs_read_cr(const struct flashctx *flash, uint32_t addr)
168{
169 uint8_t cfg;
170 /* By default, 8 dummy cycles are necessary for variable-latency
171 commands such as RDAR (see CR2NV[3:0]). */
172 uint8_t read_cr_cmd[] = {
173 CMD_RDAR,
174 (addr >> 16) & 0xff,
175 (addr >> 8) & 0xff,
176 (addr & 0xff),
177 0x00, 0x00, 0x00, 0x00,
178 0x00, 0x00, 0x00, 0x00,
179 };
180
181 int result = spi_send_command(flash, sizeof(read_cr_cmd), 1, read_cr_cmd, &cfg);
182 if (result) {
183 msg_cerr("%s failed during command execution at address 0x%x\n",
184 __func__, addr);
185 return -1;
186 }
187
188 return cfg;
189}
190
191/* "Write Any Register" instruction only supported on S25FS */
192static int s25fs_write_cr(const struct flashctx *flash,
193 uint32_t addr, uint8_t data)
194{
195 struct spi_command cmds[] = {
196 {
197 .writecnt = JEDEC_WREN_OUTSIZE,
198 .writearr = (const uint8_t[]){ JEDEC_WREN },
199 .readcnt = 0,
200 .readarr = NULL,
201 }, {
202 .writecnt = CMD_WRAR_LEN,
203 .writearr = (const uint8_t[]){
204 CMD_WRAR,
205 (addr >> 16) & 0xff,
206 (addr >> 8) & 0xff,
207 (addr & 0xff),
208 data
209 },
210 .readcnt = 0,
211 .readarr = NULL,
212 }, {
213 .writecnt = 0,
214 .writearr = NULL,
215 .readcnt = 0,
216 .readarr = NULL,
217 }};
218
219 int result = spi_send_multicommand(flash, cmds);
220 if (result) {
221 msg_cerr("%s failed during command execution at address 0x%x\n",
222 __func__, addr);
223 return -1;
224 }
225
226 programmer_delay(T_W);
227 return s25f_poll_status(flash);
228}
229
230static int s25fs_restore_cr3nv(struct flashctx *flash, uint8_t cfg)
231{
232 int ret = 0;
233
234 msg_cdbg("Restoring CR3NV value to 0x%02x\n", cfg);
235 ret |= s25fs_write_cr(flash, CR3NV_ADDR, cfg);
236 ret |= s25fs_software_reset(flash);
237 return ret;
238}
239
240int s25fs_block_erase_d8(struct flashctx *flash,
241 uint32_t addr, uint32_t blocklen)
242{
243 static int cr3nv_checked = 0;
244
245 struct spi_command erase_cmds[] = {
246 {
247 .writecnt = JEDEC_WREN_OUTSIZE,
248 .writearr = (const uint8_t[]){ JEDEC_WREN },
249 .readcnt = 0,
250 .readarr = NULL,
251 }, {
252 .writecnt = JEDEC_BE_D8_OUTSIZE,
253 .writearr = (const uint8_t[]){
254 JEDEC_BE_D8,
255 (addr >> 16) & 0xff,
256 (addr >> 8) & 0xff,
257 (addr & 0xff)
258 },
259 .readcnt = 0,
260 .readarr = NULL,
261 }, {
262 .writecnt = 0,
263 .writearr = NULL,
264 .readcnt = 0,
265 .readarr = NULL,
266 }};
267
268 /* Check if hybrid sector architecture is in use and, if so,
269 * switch to uniform sectors. */
270 if (!cr3nv_checked) {
271 uint8_t cfg = s25fs_read_cr(flash, CR3NV_ADDR);
272 if (!(cfg & CR3NV_20H_NV)) {
273 s25fs_write_cr(flash, CR3NV_ADDR, cfg | CR3NV_20H_NV);
274 s25fs_software_reset(flash);
275
276 cfg = s25fs_read_cr(flash, CR3NV_ADDR);
277 if (!(cfg & CR3NV_20H_NV)) {
278 msg_cerr("%s: Unable to enable uniform "
279 "block sizes.\n", __func__);
280 return 1;
281 }
282
283 msg_cdbg("\n%s: CR3NV updated (0x%02x -> 0x%02x)\n",
284 __func__, cfg,
285 s25fs_read_cr(flash, CR3NV_ADDR));
286 /* Restore CR3V when flashrom exits */
287 register_chip_restore(s25fs_restore_cr3nv, flash, cfg);
288 }
289
290 cr3nv_checked = 1;
291 }
292
293 int result = spi_send_multicommand(flash, erase_cmds);
294 if (result) {
295 msg_cerr("%s failed during command execution at address 0x%x\n",
296 __func__, addr);
297 return result;
298 }
299
300 programmer_delay(S25FS_T_SE);
301 return s25f_poll_status(flash);
302}
303
304int s25fl_block_erase(struct flashctx *flash,
305 uint32_t addr, uint32_t blocklen)
306{
307 struct spi_command erase_cmds[] = {
308 {
309 .writecnt = JEDEC_WREN_OUTSIZE,
310 .writearr = (const uint8_t[]){
311 JEDEC_WREN
312 },
313 .readcnt = 0,
314 .readarr = NULL,
315 }, {
316 .writecnt = JEDEC_BE_DC_OUTSIZE,
317 .writearr = (const uint8_t[]){
318 JEDEC_BE_DC,
319 (addr >> 24) & 0xff,
320 (addr >> 16) & 0xff,
321 (addr >> 8) & 0xff,
322 (addr & 0xff)
323 },
324 .readcnt = 0,
325 .readarr = NULL,
326 }, {
327 .writecnt = 0,
328 .readcnt = 0,
329 }
330 };
331
332 int result = spi_send_multicommand(flash, erase_cmds);
333 if (result) {
334 msg_cerr("%s failed during command execution at address 0x%x\n",
335 __func__, addr);
336 return result;
337 }
338
339 programmer_delay(S25FL_T_SE);
340 return s25f_poll_status(flash);
341}
342
343
344int probe_spi_big_spansion(struct flashctx *flash)
345{
346 uint8_t cmd = JEDEC_RDID;
347 uint8_t dev_id[6]; /* We care only about 6 first bytes */
348
349 if (spi_send_command(flash, sizeof(cmd), sizeof(dev_id), &cmd, dev_id))
350 return 0;
351
352 msg_gdbg("Read id bytes: ");
353 for (size_t i = 0; i < sizeof(dev_id); i++)
354 msg_gdbg(" 0x%02x", dev_id[i]);
355 msg_gdbg(".\n");
356
357 /*
358 * The structure of the RDID output is as follows:
359 *
360 * offset value meaning
361 * 00h 01h Manufacturer ID for Spansion
362 * 01h 20h 128 Mb capacity
363 * 01h 02h 256 Mb capacity
364 * 02h 18h 128 Mb capacity
365 * 02h 19h 256 Mb capacity
366 * 03h 4Dh Full size of the RDID output (ignored)
367 * 04h 00h FS: 256-kB physical sectors
368 * 04h 01h FS: 64-kB physical sectors
369 * 04h 00h FL: 256-kB physical sectors
370 * 04h 01h FL: Mix of 64-kB and 4KB overlayed sectors
371 * 05h 80h FL family
372 * 05h 81h FS family
373 *
374 * Need to use bytes 1, 2, 4, and 5 to properly identify one of eight
375 * possible chips:
376 *
377 * 2 types * 2 possible sizes * 2 possible sector layouts
378 *
379 */
380
381 uint32_t model_id =
382 dev_id[1] << 24 |
383 dev_id[2] << 16 |
384 dev_id[4] << 8 |
385 dev_id[5] << 0;
386
387 if (dev_id[0] == flash->chip->manufacture_id && model_id == flash->chip->model_id)
388 return 1;
389
390 return 0;
391}