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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000027#include <strings.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000029#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000034#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000036 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000037 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000038/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000039void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040{
Andriy Gapon65c1b862008-05-22 13:22:45 +000041 OUTB(0x87, port);
42 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000044
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000046void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000047{
Andriy Gapon65c1b862008-05-22 13:22:45 +000048 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000050
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051/* Generic Super I/O helper functions */
52uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054 OUTB(reg, port);
55 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000057
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060 OUTB(reg, port);
61 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000065{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000066 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000068 OUTB(reg, port);
69 tmp = INB(port + 1) & ~mask;
70 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000071}
72
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000073/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
74void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
75{
76 uint8_t tmp;
77
78 OUTB(reg, port);
79 tmp = INB(port + 1) & ~mask;
80 OUTB(reg, port);
81 OUTB(tmp | (data & mask), port + 1);
82}
83
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084/* Not used yet. */
85#if 0
86static int enable_flash_decode_superio(void)
87{
88 int ret;
89 uint8_t tmp;
90
91 switch (superio.vendor) {
92 case SUPERIO_VENDOR_NONE:
93 ret = -1;
94 break;
95 case SUPERIO_VENDOR_ITE:
96 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000097 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000098 tmp = sio_read(superio.port, 0x24);
99 tmp |= 0xfc;
100 sio_write(superio.port, 0x24, tmp);
101 exit_conf_mode_ite(superio.port);
102 ret = 0;
103 break;
104 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000105 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000106 ret = -1;
107 break;
108 }
109 return ret;
110}
111#endif
112
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000113/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000114 * SMSC FDC37B787: Raise GPIO50
115 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000116static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000117{
118 uint8_t id, val;
119
120 OUTB(0x55, port); /* enter conf mode */
121 id = sio_read(port, 0x20);
122 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000123 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000124 OUTB(0xAA, port); /* leave conf mode */
125 return -1;
126 }
127
128 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
129
130 val = sio_read(port, 0xC8); /* GP50 */
131 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
132 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000133 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000134 OUTB(0xAA, port);
135 return -1;
136 }
137
138 sio_mask(port, 0xF9, 0x01, 0x01);
139
140 OUTB(0xAA, port); /* Leave conf mode */
141 return 0;
142}
143
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000144/*
145 * Suited for:
146 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000148static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000149{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000150 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000151}
152
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000153struct winbond_mux {
154 uint8_t reg; /* 0 if the corresponding pin is not muxed */
155 uint8_t data; /* reg/data/mask may be directly ... */
156 uint8_t mask; /* ... passed to sio_mask */
157};
158
159struct winbond_port {
160 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
161 uint8_t ldn; /* LDN this GPIO register is located in */
162 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
163 the GPIO port */
164 uint8_t base; /* base register in that LDN for the port */
165};
166
167struct winbond_chip {
168 uint8_t device_id; /* reg 0x20 of the expected w83626x */
169 uint8_t gpio_port_count;
170 const struct winbond_port *port;
171};
172
173
174#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
175
176enum winbond_id {
177 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000178 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000179 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000180 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000181};
182
183static const struct winbond_mux w83627hf_port2_mux[8] = {
184 {0x2A, 0x01, 0x01}, /* or MIDI */
185 {0x2B, 0x80, 0x80}, /* or SPI */
186 {0x2B, 0x40, 0x40}, /* or SPI */
187 {0x2B, 0x20, 0x20}, /* or power LED */
188 {0x2B, 0x10, 0x10}, /* or watchdog */
189 {0x2B, 0x08, 0x08}, /* or infra red */
190 {0x2B, 0x04, 0x04}, /* or infra red */
191 {0x2B, 0x03, 0x03} /* or IRQ1 input */
192};
193
194static const struct winbond_port w83627hf[3] = {
195 UNIMPLEMENTED_PORT,
196 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000197 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000198};
199
Michael Karcherea36c9c2010-06-27 15:07:52 +0000200static const struct winbond_mux w83627ehf_port2_mux[8] = {
201 {0x29, 0x06, 0x02}, /* or MIDI */
202 {0x29, 0x06, 0x02},
203 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
204 {0x24, 0x02, 0x00},
205 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
206 {0x2A, 0x01, 0x01},
207 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000208 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000209};
210
211static const struct winbond_port w83627ehf[6] = {
212 UNIMPLEMENTED_PORT,
213 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
214 UNIMPLEMENTED_PORT,
215 UNIMPLEMENTED_PORT,
216 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000217 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000218};
219
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000220static const struct winbond_mux w83627thf_port4_mux[8] = {
221 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
222 {0x2D, 0x02, 0x02}, /* or resume reset */
223 {0x2D, 0x04, 0x04}, /* or S3 input */
224 {0x2D, 0x08, 0x08}, /* or PSON# */
225 {0x2D, 0x10, 0x10}, /* or PWROK */
226 {0x2D, 0x20, 0x20}, /* or suspend LED */
227 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000228 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000229};
230
231static const struct winbond_port w83627thf[5] = {
232 UNIMPLEMENTED_PORT, /* GPIO1 */
233 UNIMPLEMENTED_PORT, /* GPIO2 */
234 UNIMPLEMENTED_PORT, /* GPIO3 */
235 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000236 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000237};
238
239static const struct winbond_chip winbond_chips[] = {
240 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000241 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000242 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
243};
244
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000245#define WINBOND_SUPERIO_PORT1 0x2e
246#define WINBOND_SUPERIO_PORT2 0x4e
247
248/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
249 * the simple device ID in the normal configuration registers.
250 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000251 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000252static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000253{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000254 uint16_t hwmport;
255 uint16_t hwm_vendorid;
256 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000257
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000258 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
259 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
260 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
261 return 0;
262 }
263 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
264 hwmport = sio_read(sio_port, 0x60) << 8;
265 hwmport |= sio_read(sio_port, 0x61);
266 /* HWM address register = HWM base address + 5. */
267 hwmport += 5;
268 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
269 /* FIXME: This busy check should happen before each HWM access. */
270 if (INB(hwmport) & 0x80) {
271 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
272 return 0;
273 }
274 /* Set HBACS=1. */
275 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
276 /* Read upper byte of vendor ID. */
277 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
278 /* Set HBACS=0. */
279 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
280 /* Read lower byte of vendor ID. */
281 hwm_vendorid |= sio_read(hwmport, 0x4f);
282 if (hwm_vendorid != 0x5ca3) {
283 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
284 hwm_vendorid);
285 return 0;
286 }
287 /* Set Bank=0. */
288 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
289 /* Read "chip" ID. We call this one the device ID. */
290 hwm_deviceid = sio_read(hwmport, 0x58);
291 return hwm_deviceid;
292}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000294void probe_superio_winbond(void)
295{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000296 struct superio s = {0};
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000297 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
298 uint16_t *i = winbond_ports;
299 uint8_t model;
300 uint8_t tmp;
301
302 s.vendor = SUPERIO_VENDOR_WINBOND;
303 for (; *i; i++) {
304 s.port = *i;
305 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
306 w836xx_ext_enter(s.port);
307 model = sio_read(s.port, 0x20);
308 /* No response, no point leaving the config mode. */
309 if (model == 0xff)
310 continue;
311 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
312 w836xx_ext_leave(s.port);
313 if (model == sio_read(s.port, 0x20)) {
314 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
315 "leave config mode had no effect.\n");
316 if (model == 0x87) {
317 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
318 * but they want the ITE exit sequence. Handle them here.
319 */
320 tmp = sio_read(s.port, 0x21);
321 switch (tmp) {
322 case 0x07:
323 case 0x10:
324 s.vendor = SUPERIO_VENDOR_ITE;
325 s.model = (0x87 << 8) | tmp ;
326 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
327 "0x%x\n", s.model, s.port);
328 register_superio(s);
329 /* Exit ITE config mode. */
330 exit_conf_mode_ite(s.port);
331 /* Restore vendor for next loop iteration. */
332 s.vendor = SUPERIO_VENDOR_WINBOND;
333 continue;
334 }
335 }
Stefan Tauner23e10b82016-01-23 16:16:49 +0000336 msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000337 continue;
Stefan Tauner23e10b82016-01-23 16:16:49 +0000338 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000339 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
340 w836xx_ext_enter(s.port);
341 s.model = sio_read(s.port, 0x20);
342 switch (s.model) {
343 case WINBOND_W83627HF_ID:
344 case WINBOND_W83627EHF_ID:
345 case WINBOND_W83627THF_ID:
Stefan Taunereb582572012-09-21 12:52:50 +0000346 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000347 register_superio(s);
348 break;
349 case WINBOND_W83697HF_ID:
350 /* This code is extremely paranoid. */
351 tmp = sio_read(s.port, 0x26) & 0x40;
352 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
353 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
354 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
Stefan Taunereb582572012-09-21 12:52:50 +0000355 "0x%02x at port 0x%04x\n", s.model, s.port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000356 break;
357 }
358 tmp = w836xx_deviceid_hwmon(s.port);
359 /* FIXME: This might be too paranoid... */
360 if (!tmp) {
361 msg_pdbg("Probably not a Winbond Super I/O\n");
362 break;
363 }
364 if (tmp != s.model) {
Stefan Taunereb582572012-09-21 12:52:50 +0000365 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
366 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000367 break;
368 }
Stefan Taunereb582572012-09-21 12:52:50 +0000369 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000370 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000371 break;
372 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000373 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000374 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000375 return;
376}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000377
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000378static const struct winbond_chip *winbond_superio_chipdef(void)
379{
380 int i, j;
381
382 for (i = 0; i < superio_count; i++) {
383 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
384 continue;
385 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
386 if (winbond_chips[j].device_id == superios[i].model)
387 return &winbond_chips[j];
388 }
389 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000390}
391
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000392/*
393 * The chipid parameter goes away as soon as we have Super I/O matching in the
394 * board enable table. The call to winbond_superio_detect() goes away as
395 * soon as we have generic Super I/O detection code.
396 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000397static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
398 int pin, int raise)
399{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000400 const struct winbond_chip *chip = NULL;
401 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000402 int port = pin / 10;
403 int bit = pin % 10;
404
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000405 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000406 if (!chip) {
407 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
408 return -1;
409 }
Michael Karcher979d9252010-06-29 14:44:40 +0000410 if (chip->device_id != chipid) {
411 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
412 "expected %x\n", chip->device_id, chipid);
413 return -1;
414 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000415 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
416 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
417 pin);
418 return -1;
419 }
420
421 gpio = &chip->port[port - 1];
422
423 if (gpio->ldn == 0) {
424 msg_perr("\nERROR: GPIO%d is not supported yet on this"
425 " winbond chip\n", port);
426 return -1;
427 }
428
429 w836xx_ext_enter(base);
430
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000431 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000432 sio_write(base, 0x07, gpio->ldn);
433
434 /* Activate logical device. */
435 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
436
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000437 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000438 if (gpio->mux && gpio->mux[bit].reg)
439 sio_mask(base, gpio->mux[bit].reg,
440 gpio->mux[bit].data, gpio->mux[bit].mask);
441
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000442 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000443 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
444 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
445
446 w836xx_ext_leave(base);
447
448 return 0;
449}
450
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000451/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000452 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000453 *
454 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000455 * - Agami Aruma
456 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000457 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000458static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000459{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000460 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000461}
462
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000463/*
Joshua Roysf280a382010-08-07 21:49:11 +0000464 * Winbond W83627HF: Raise GPIO25.
465 *
466 * Suited for:
467 * - MSI MS-6577
468 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000469static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000470{
471 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
472}
473
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000474/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000475 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000476 *
477 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000478 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000479 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000480static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000481{
Stefan Taunerff80e682011-07-20 16:34:18 +0000482 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000483}
484
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000485/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000486 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000487 *
488 * Suited for:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000489 * - MSI K8T Neo2-F V2.0
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000490 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000491static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000492{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000493 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000494}
495
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000496/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000497 * Winbond W83627THF: Raise GPIO 44.
498 *
499 * Suited for:
500 * - MSI K8N Neo3
501 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000502static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000503{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000504 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000505}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000506
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000507/*
David Borgb6417a62010-08-02 08:29:34 +0000508 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000509 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000510 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000511static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000512{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513 w836xx_ext_enter(port);
514 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000515 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000516 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000517 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000518 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000519}
520
David Borgb02c62b2012-05-05 20:43:42 +0000521/**
522 * Enable MEMW# and set ROM size to max.
523 * Supported chips:
524 * W83697HF/F/HG, W83697SF/UF/UG
525 */
526void w83697xx_memw_enable(uint16_t port)
527{
528 w836xx_ext_enter(port);
529 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
530 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
531
532 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
533 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
534 /* These bits are reserved on W83697HF/F/HG */
535 /* Shouldn't be needed though. */
536
537 /* CR28 Bit3 must be set to 1 to enable flash access to */
538 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
539 /* This bit is reserved on W83697HF/F/HG which default to 0 */
540 sio_mask(port, 0x28, 0x08, 0x08);
541
542 /* Enable MEMW# and set ROM size select to max. (4M)*/
543 sio_mask(port, 0x24, 0x28, 0x38);
544
545 } else {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000546 msg_pwarn("Warning: Flash interface in use by GPIO!\n");
David Borgb02c62b2012-05-05 20:43:42 +0000547 }
548 } else {
549 msg_pinfo("BIOS ROM is disabled\n");
550 }
551 w836xx_ext_leave(port);
552}
553
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000554/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000555 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000556 * - Biostar M7VIQ: VIA KM266 + VT8235
557 */
558static int w83697xx_memw_enable_2e(void)
559{
560 w83697xx_memw_enable(0x2E);
561
562 return 0;
563}
564
565
566/*
567 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000568 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000569 * - EPoX EP-8K5A2: VIA KT333 + VT8235
570 * - Albatron PM266A Pro: VIA P4M266A + VT8235
571 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
572 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
573 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000574 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000575 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000576 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000577 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000578 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000579 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000580static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000581{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000582 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000583
Luc Verhaegen73d21192009-12-23 00:54:26 +0000584 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000585}
586
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000587/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000588 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000589 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000590 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000591static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000592{
593 w836xx_memw_enable(0x4E);
594
595 return 0;
596}
597
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000598/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000599 * Suited for all boards with ITE IT8705F.
600 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000601 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000602int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000603{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000604 uint8_t tmp;
605 int ret = 0;
606
Luc Verhaegen21f54962010-01-20 14:45:07 +0000607 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000608 tmp = sio_read(port, 0x24);
609 /* Check if at least one flash segment is enabled. */
610 if (tmp & 0xf0) {
611 /* The IT8705F will respond to LPC cycles and translate them. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000612 internal_buses_supported = BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000613 /* Flash ROM I/F Writes Enable */
614 tmp |= 0x04;
615 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
616 if (tmp & 0x02) {
617 /* The data sheet contradicts itself about max size. */
618 max_rom_decode.parallel = 1024 * 1024;
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000619 msg_pinfo("IT8705F with very unusual settings.\n"
620 "Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
621 "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000622 "support for your Super I/O. Thanks.\n");
623 ret = 1;
624 } else if (tmp & 0x08) {
625 max_rom_decode.parallel = 512 * 1024;
626 } else {
627 max_rom_decode.parallel = 256 * 1024;
628 }
629 /* Safety checks. The data sheet is unclear here: Segments 1+3
630 * overlap, no segment seems to cover top - 1MB to top - 512kB.
631 * We assume that certain combinations make no sense.
632 */
633 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
634 (!(tmp & 0x10)) || /* 128 kB dis */
635 (!(tmp & 0x40))) { /* 256/512 kB dis */
636 msg_perr("Inconsistent IT8705F decode size!\n");
637 ret = 1;
638 }
639 if (sio_read(port, 0x25) != 0) {
640 msg_perr("IT8705F flash data pins disabled!\n");
641 ret = 1;
642 }
643 if (sio_read(port, 0x26) != 0) {
644 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
645 ret = 1;
646 }
647 if (sio_read(port, 0x27) != 0) {
648 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
649 ret = 1;
650 }
651 if ((sio_read(port, 0x29) & 0x10) != 0) {
652 msg_perr("IT8705F flash write enable pin disabled!\n");
653 ret = 1;
654 }
655 if ((sio_read(port, 0x29) & 0x08) != 0) {
656 msg_perr("IT8705F flash chip select pin disabled!\n");
657 ret = 1;
658 }
659 if ((sio_read(port, 0x29) & 0x04) != 0) {
660 msg_perr("IT8705F flash read strobe pin disabled!\n");
661 ret = 1;
662 }
663 if ((sio_read(port, 0x29) & 0x03) != 0) {
664 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
665 /* Not really an error if you use flash chips smaller
666 * than 256 kByte, but such a configuration is unlikely.
667 */
668 ret = 1;
669 }
670 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
671 max_rom_decode.parallel);
672 if (ret) {
673 msg_pinfo("Not enabling IT8705F flash write.\n");
674 } else {
675 sio_write(port, 0x24, tmp);
676 }
677 } else {
678 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000679 ret = 0;
680 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000681 exit_conf_mode_ite(port);
682
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000683 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000684}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000685
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000686/*
687 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
688 * It uses the Winbond command sequence to enter extended configuration
689 * mode and the ITE sequence to exit.
690 *
691 * Registers seems similar to the ones on ITE IT8710F.
692 */
693static int it8707f_write_enable(uint8_t port)
694{
695 uint8_t tmp;
696
697 w836xx_ext_enter(port);
698
699 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
700 tmp = sio_read(port, 0x23);
701 tmp |= (1 << 3);
702 sio_write(port, 0x23, tmp);
703
704 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
705 tmp = sio_read(port, 0x24);
706 tmp |= (1 << 2) | (1 << 3);
707 sio_write(port, 0x24, tmp);
708
709 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
710 tmp = sio_read(port, 0x23);
711 tmp &= ~(1 << 3);
712 sio_write(port, 0x23, tmp);
713
714 exit_conf_mode_ite(port);
715
716 return 0;
717}
718
719/*
720 * Suited for:
721 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
722 */
723static int it8707f_write_enable_2e(void)
724{
725 return it8707f_write_enable(0x2e);
726}
727
Michael Karchercba52de2011-03-06 12:07:19 +0000728#define PC87360_ID 0xE1
729#define PC87364_ID 0xE4
730
731static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000732{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000733 static const int bankbase[] = {0, 4, 8, 10, 12};
734 int gpio_bank = gpio / 8;
735 int gpio_pin = gpio % 8;
736 uint16_t baseport;
737 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000738
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000739 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000740 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000741 return -1;
742 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000743
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000745 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000746 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
747 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000748 return -1;
749 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000750
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000751 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
752 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
753 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
754 msg_perr("PC87360: invalid GPIO base address %04x\n",
755 baseport);
756 return -1;
757 }
758 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
759 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
760 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000761
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000762 val = INB(baseport + bankbase[gpio_bank]);
763 if (raise)
764 val |= 1 << gpio_pin;
765 else
766 val &= ~(1 << gpio_pin);
767 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000768
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000769 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000770}
771
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000772/*
773 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000774 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000775static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000776{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000777 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000778 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000779 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000780
Luc Verhaegen73d21192009-12-23 00:54:26 +0000781 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
782 switch (dev->device_id) {
783 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000784 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000785 case 0x3337: /* VT8237A */
786 break;
787 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000788 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000789 return -1;
790 }
791
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000792 if ((gpio >= 12) && (gpio <= 15)) {
793 /* GPIO12-15 -> output */
794 val = pci_read_byte(dev, 0xE4);
795 val |= 0x10;
796 pci_write_byte(dev, 0xE4, val);
797 } else if (gpio == 9) {
798 /* GPIO9 -> Output */
799 val = pci_read_byte(dev, 0xE4);
800 val |= 0x20;
801 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000802 } else if (gpio == 5) {
803 val = pci_read_byte(dev, 0xE4);
804 val |= 0x01;
805 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000806 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000807 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000808 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000809 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000810 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000811
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000812 /* We need the I/O Base Address for this board's flash enable. */
813 base = pci_read_word(dev, 0x88) & 0xff80;
814
David Bartleyf58d3642009-12-09 07:53:01 +0000815 offset = 0x4C + gpio / 8;
816 bit = 0x01 << (gpio % 8);
817
818 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000819 if (raise)
820 val |= bit;
821 else
822 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000823 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000824
Uwe Hermanna7e05482007-05-09 10:17:44 +0000825 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000826}
827
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000828/*
829 * Suited for:
830 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000831 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000832static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000833{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000834 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
835 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000836}
837
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000838/*
839 * Suited for:
840 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000841 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000842static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000843{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000844 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000845}
846
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000847/*
848 * Suited for:
849 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000850 *
851 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
852 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000853 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000854static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000855{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000856 return via_vt823x_gpio_set(15, 1);
857}
858
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000859/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000860 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
861 *
862 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000863 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
864 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000865 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000866static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000867{
868 int ret;
869
870 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000871 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000872
Luc Verhaegen73d21192009-12-23 00:54:26 +0000873 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000874}
875
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000876/*
877 * Suited for:
878 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000879 *
880 * This is rather nasty code, but there's no way to do this cleanly.
881 * We're basically talking to some unknown device on SMBus, my guess
882 * is that it is the Winbond W83781D that lives near the DIP BIOS.
883 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000884static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000885{
886 uint8_t tmp;
887 int i;
888
889#define ASUSP5A_LOOP 5000
890
Andriy Gapon65c1b862008-05-22 13:22:45 +0000891 OUTB(0x00, 0xE807);
892 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000893
Andriy Gapon65c1b862008-05-22 13:22:45 +0000894 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000895
896 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000897 OUTB(0xE1, 0xFF);
898 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000899 break;
900 }
901
902 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000903 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000904 return -1;
905 }
906
Andriy Gapon65c1b862008-05-22 13:22:45 +0000907 OUTB(0x20, 0xE801);
908 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000909
Andriy Gapon65c1b862008-05-22 13:22:45 +0000910 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000911
912 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000913 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000914 if (tmp & 0x70)
915 break;
916 }
917
918 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000919 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000920 return -1;
921 }
922
Andriy Gapon65c1b862008-05-22 13:22:45 +0000923 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000924 tmp &= ~0x02;
925
Andriy Gapon65c1b862008-05-22 13:22:45 +0000926 OUTB(0x00, 0xE807);
927 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000928
Andriy Gapon65c1b862008-05-22 13:22:45 +0000929 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000930
Andriy Gapon65c1b862008-05-22 13:22:45 +0000931 OUTB(0xFF, 0xE800);
932 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000933
Andriy Gapon65c1b862008-05-22 13:22:45 +0000934 OUTB(0x20, 0xE801);
935 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000936
Andriy Gapon65c1b862008-05-22 13:22:45 +0000937 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000938
939 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000940 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000941 if (tmp & 0x70)
942 break;
943 }
944
945 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000946 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000947 return -1;
948 }
949
950 return 0;
951}
952
Luc Verhaegena7e30502009-12-09 11:39:02 +0000953/*
954 * Set GPIO lines in the Broadcom HT-1000 southbridge.
955 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000956 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000957 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000958static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000959{
960 /* GPIO 0 reg from PM regs */
961 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
962 sio_mask(0xcd6, 0x44, 0x24, 0x24);
963
964 return 0;
965}
966
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000967/*
968 * Set GPIO lines in the Broadcom HT-1000 southbridge.
969 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000970 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000971 */
972static int board_hp_dl165_g6_enable(void)
973{
974 /* Variant of DL145, with slightly different pin placement. */
975 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
976 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
977
978 return 0;
979}
980
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000981static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000982{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000983 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000984 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000985
986 return 0;
987}
988
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000989/*
990 * Suited for:
Mattias Mattssonf4925162010-09-16 22:09:18 +0000991 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
992 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000993static int board_ecs_geforce6100sm_m(void)
994{
995 struct pci_dev *dev;
996 uint32_t tmp;
997
998 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
999 if (!dev) {
1000 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1001 return -1;
1002 }
1003
1004 tmp = pci_read_byte(dev, 0xE0);
1005 tmp &= ~(1 << 3);
1006 pci_write_byte(dev, 0xE0, tmp);
1007
1008 return 0;
1009}
1010
1011/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001012 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001013 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001014static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001015{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001016 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001017 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001018 uint8_t tmp;
1019
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001020 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001021 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001022 return -1;
1023 }
1024
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001025 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001026 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001027 switch (dev->device_id) {
1028 case 0x0030: /* CK804 */
1029 case 0x0050: /* MCP04 */
1030 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001031 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001032 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001033 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001034 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001035 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001036 case 0x0364: /* MCP55 */
1037 /* find SMBus controller on *this* southbridge */
1038 /* The infamous Tyan S2915-E has two south bridges; they are
1039 easily told apart from each other by the class of the
1040 LPC bridge, but have the same SMBus bridge IDs */
1041 if (dev->func != 0) {
1042 msg_perr("MCP LPC bridge at unexpected function"
1043 " number %d\n", dev->func);
1044 return -1;
1045 }
1046
Stefan Tauner56734502015-02-08 21:58:04 +00001047#if !defined(OLD_PCI_GET_DEV)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001048 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001049#else
1050 /* pciutils/libpci before version 2.2 is too old to support
1051 * PCI domains. Such old machines usually don't have domains
1052 * besides domain 0, so this is not a problem.
1053 */
1054 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1055#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001056 if (!dev) {
1057 msg_perr("MCP SMBus controller could not be found\n");
1058 return -1;
1059 }
1060 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1061 if (devclass != 0x0C05) {
1062 msg_perr("Unexpected device class %04x for SMBus"
1063 " controller\n", devclass);
1064 return -1;
1065 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001066 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001067 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001068 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001069 return -1;
1070 }
1071
1072 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1073 base += 0xC0;
1074
1075 tmp = INB(base + gpio);
1076 tmp &= ~0x0F; /* null lower nibble */
1077 tmp |= 0x04; /* gpio -> output. */
1078 if (raise)
1079 tmp |= 0x01;
1080 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001081
1082 return 0;
1083}
1084
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001085/*
1086 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001087 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001088 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001089 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001090 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001091static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001092{
1093 return nvidia_mcp_gpio_set(0x00, 1);
1094}
1095
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001096/*
1097 * Suited for:
1098 * - abit KN8 Ultra: NVIDIA CK804
Stefan Tauner74dc73f2015-03-01 22:04:38 +00001099 * - abit KN9 Ultra: NVIDIA MCP55
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001100 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001101static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001102{
1103 return nvidia_mcp_gpio_set(0x02, 0);
1104}
1105
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001106/*
1107 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001108 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001109 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
Uwe Hermannead705f2010-08-15 15:26:30 +00001110 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001111 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001112 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001113static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001114{
1115 return nvidia_mcp_gpio_set(0x02, 1);
1116}
1117
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001118/*
1119 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001120 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001121 */
1122static int nvidia_mcp_gpio4_raise(void)
1123{
1124 return nvidia_mcp_gpio_set(0x04, 1);
1125}
1126
1127/*
1128 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001129 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1130 *
1131 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1132 * board. We can't tell the SMBus logical devices apart, but we
1133 * can tell the LPC bridge functions apart.
1134 * We need to choose the SMBus bridge next to the LPC bridge with
1135 * ID 0x364 and the "LPC bridge" class.
1136 * b) #TBL is hardwired on that board to a pull-down. It can be
1137 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001138 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001139static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001140{
1141 return nvidia_mcp_gpio_set(0x05, 1);
1142}
1143
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001144/*
1145 * Suited for:
1146 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001147 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001148static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001149{
1150 return nvidia_mcp_gpio_set(0x08, 1);
1151}
1152
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001153/*
1154 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001155 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Stefan Tauner23e10b82016-01-23 16:16:49 +00001156 * - Probably other versions of the GA-K8NS
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001157 */
1158static int nvidia_mcp_gpio0a_raise(void)
1159{
1160 return nvidia_mcp_gpio_set(0x0a, 1);
1161}
1162
1163/*
1164 * Suited for:
Stefan Tauner33366a02012-09-15 15:51:09 +00001165 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001166 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001167 */
Michael Karcher51825082010-06-12 23:14:03 +00001168static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001169{
1170 return nvidia_mcp_gpio_set(0x0c, 1);
1171}
1172
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001173/*
1174 * Suited for:
1175 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001176 */
1177static int nvidia_mcp_gpio4_lower(void)
1178{
1179 return nvidia_mcp_gpio_set(0x04, 0);
1180}
1181
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001182/*
1183 * Suited for:
1184 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001185 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001186static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001187{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001188 return nvidia_mcp_gpio_set(0x10, 1);
1189}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001190
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001191/*
1192 * Suited for:
1193 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001194 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001195static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001196{
1197 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001198}
1199
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001200/*
1201 * Suited for:
1202 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001203 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001204static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001205{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001206 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001207}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001208
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001209/*
1210 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001211 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1212 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001213 */
1214static int nvidia_mcp_gpio3b_raise(void)
1215{
1216 return nvidia_mcp_gpio_set(0x3b, 1);
1217}
1218
1219/*
1220 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001221 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1222 */
1223static int board_sun_ultra_40_m2(void)
1224{
1225 int ret;
1226 uint8_t reg;
1227 uint16_t base;
1228 struct pci_dev *dev;
1229
1230 ret = nvidia_mcp_gpio4_lower();
1231 if (ret)
1232 return ret;
1233
1234 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1235 if (!dev) {
1236 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1237 return -1;
1238 }
1239
1240 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1241 if (!base)
1242 return -1;
1243
1244 reg = INB(base + 0x4b);
1245 reg |= 0x10;
1246 OUTB(reg, base + 0x4b);
1247
1248 return 0;
1249}
1250
1251/*
1252 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001253 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001254 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001255static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001256{
1257#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001258#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1259#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1260#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001261#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1262#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1263#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001264#define DBE6x_BOOT_LOC_FLASH 2
1265#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001266
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001267 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001268 unsigned long boot_loc;
1269
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001270 /* Geode only has a single core */
1271 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001272 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001273
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001274 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001275
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001276 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001277 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1278 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1279 else
1280 boot_loc = DBE6x_BOOT_LOC_FLASH;
1281
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001282 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1283 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001284 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001285
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001286 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001287
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001288 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001289
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001290 return 0;
1291}
1292
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001293/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001294 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001295 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001296 * Datasheet(s) used:
1297 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1298 */
1299static int amd_sbxxx_gpio9_raise(void)
1300{
1301 struct pci_dev *dev;
1302 uint32_t reg;
1303
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001304 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001305 if (!dev) {
1306 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1307 return -1;
1308 }
1309
1310 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1311 /* enable output (0: enable, 1: tristate):
1312 GPIO9 output enable is at bit 5 in 0xA9 */
1313 reg &= ~((uint32_t)1<<(8+5));
1314 /* raise:
1315 GPIO9 output register is at bit 5 in 0xA8 */
1316 reg |= (1<<5);
1317 pci_write_long(dev, 0xA8, reg);
1318
1319 return 0;
1320}
1321
1322/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001323 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001324 */
1325static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1326{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001327 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001328 struct pci_dev *dev;
1329 uint32_t tmp, base;
1330
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001331 /* GPO{0,8,27,28,30} are always available. */
1332 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001333
1334 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001335 {0},
1336 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1337 {0xB0, 0x0001, 0x0000},
1338 {0xB0, 0x0001, 0x0000},
1339 {0xB0, 0x0001, 0x0000},
1340 {0xB0, 0x0001, 0x0000},
1341 {0xB0, 0x0001, 0x0000},
1342 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1343 {0},
1344 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1345 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1346 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1347 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1348 {0x4E, 0x0100, 0x0000},
1349 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1350 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1351 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1352 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1353 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1354 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1355 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1356 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1357 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1358 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1359 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1360 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1361 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1362 {0},
1363 {0},
1364 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1365 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001366 };
1367
Luc Verhaegenf5226912009-12-14 10:41:58 +00001368 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1369 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001370 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001371 return -1;
1372 }
1373
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001374 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001375 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001376 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001377 return -1;
1378 }
1379
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001380 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001381 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1382 piix4_gpo[gpo].value)) {
1383 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001384 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001385 }
1386
Luc Verhaegenf5226912009-12-14 10:41:58 +00001387 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1388 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001389 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001390 return -1;
1391 }
1392
1393 /* PM IO base */
1394 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1395
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001396 gpo_byte = gpo >> 3;
1397 gpo_bit = gpo & 7;
1398 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001399 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001400 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001401 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001402 tmp &= ~(0x01 << gpo_bit);
1403 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001404
1405 return 0;
1406}
1407
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001408/*
1409 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001410 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001411 * - ASUS P2B-N
1412 */
1413static int intel_piix4_gpo18_lower(void)
1414{
1415 return intel_piix4_gpo_set(18, 0);
1416}
1417
1418/*
1419 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001420 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1421 */
1422static int intel_piix4_gpo14_raise(void)
1423{
1424 return intel_piix4_gpo_set(14, 1);
1425}
1426
1427/*
1428 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001429 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001430 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001431static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001432{
1433 return intel_piix4_gpo_set(22, 1);
1434}
1435
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001436/*
1437 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001438 * - abit BM6
1439 */
1440static int intel_piix4_gpo26_lower(void)
1441{
1442 return intel_piix4_gpo_set(26, 0);
1443}
1444
1445/*
1446 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001447 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001448 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001449static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001450{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001451 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001452}
1453
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001454/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001455 * Suited for:
1456 * - Dell OptiPlex GX1
1457 */
1458static int intel_piix4_gpo30_lower(void)
1459{
1460 return intel_piix4_gpo_set(30, 0);
1461}
1462
1463/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001464 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001465 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001466static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001467{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001468 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001469 static struct {
1470 uint16_t id;
1471 uint8_t base_reg;
1472 uint32_t bank0;
1473 uint32_t bank1;
1474 uint32_t bank2;
1475 } intel_ich_gpio_table[] = {
1476 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1477 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1478 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1479 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1480 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1481 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1482 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1483 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1484 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1485 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1486 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1487 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001488 {0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001489 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1490 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1491 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1492 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1493 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1494 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1495 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1496 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1497 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1498 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1499 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1500 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1501 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1502 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1503 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1504 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1505 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1506 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1507 {0, 0, 0, 0, 0} /* end marker */
1508 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001509
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001510 struct pci_dev *dev;
1511 uint16_t base;
1512 uint32_t tmp;
1513 int i, allowed;
1514
1515 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001516 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001517 uint16_t device_class;
1518 /* libpci before version 2.2.4 does not store class info. */
1519 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001520 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001521 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001522 /* Is this device in our list? */
1523 for (i = 0; intel_ich_gpio_table[i].id; i++)
1524 if (dev->device_id == intel_ich_gpio_table[i].id)
1525 break;
1526
1527 if (intel_ich_gpio_table[i].id)
1528 break;
1529 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001530 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001531
Uwe Hermann93f66db2008-05-22 21:19:38 +00001532 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001533 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001534 return -1;
1535 }
1536
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001537 /*
1538 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1539 * strapped to zero. From some mobile ICH9 version on, this becomes
1540 * 6:1. The mask below catches all.
1541 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001542 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001543
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001544 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001545 if (gpio < 32)
1546 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1547 else if (gpio < 64)
1548 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1549 else
1550 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1551
1552 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001553 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1554 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001555 return -1;
1556 }
1557
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001558 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1559 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001560
1561 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001562 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001563 tmp = INL(base);
1564 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1565 if ((gpio == 28) &&
1566 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1567 tmp |= 1 << 27;
1568 else
1569 tmp |= 1 << gpio;
1570 OUTL(tmp, base);
1571
1572 /* As soon as we are talking to ICH8 and above, this register
1573 decides whether we can set the gpio or not. */
1574 if (dev->device_id > 0x2800) {
1575 tmp = INL(base);
1576 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001577 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001578 " does not allow setting GPIO%02d\n",
1579 gpio);
1580 return -1;
1581 }
1582 }
1583
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001584 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001585 tmp = INL(base + 0x04);
1586 tmp &= ~(1 << gpio);
1587 OUTL(tmp, base + 0x04);
1588
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001589 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001590 tmp = INL(base + 0x0C);
1591 if (raise)
1592 tmp |= 1 << gpio;
1593 else
1594 tmp &= ~(1 << gpio);
1595 OUTL(tmp, base + 0x0C);
1596 } else if (gpio < 64) {
1597 gpio -= 32;
1598
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001599 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001600 tmp = INL(base + 0x30);
1601 tmp |= 1 << gpio;
1602 OUTL(tmp, base + 0x30);
1603
1604 /* As soon as we are talking to ICH8 and above, this register
1605 decides whether we can set the gpio or not. */
1606 if (dev->device_id > 0x2800) {
1607 tmp = INL(base + 30);
1608 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001609 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001610 " does not allow setting GPIO%02d\n",
1611 gpio + 32);
1612 return -1;
1613 }
1614 }
1615
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001616 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001617 tmp = INL(base + 0x34);
1618 tmp &= ~(1 << gpio);
1619 OUTL(tmp, base + 0x34);
1620
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001621 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001622 tmp = INL(base + 0x38);
1623 if (raise)
1624 tmp |= 1 << gpio;
1625 else
1626 tmp &= ~(1 << gpio);
1627 OUTL(tmp, base + 0x38);
1628 } else {
1629 gpio -= 64;
1630
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001631 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001632 tmp = INL(base + 0x40);
1633 tmp |= 1 << gpio;
1634 OUTL(tmp, base + 0x40);
1635
1636 tmp = INL(base + 40);
1637 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001638 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001639 "not allow setting GPIO%02d\n", gpio + 64);
1640 return -1;
1641 }
1642
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001643 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001644 tmp = INL(base + 0x44);
1645 tmp &= ~(1 << gpio);
1646 OUTL(tmp, base + 0x44);
1647
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001648 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001649 tmp = INL(base + 0x48);
1650 if (raise)
1651 tmp |= 1 << gpio;
1652 else
1653 tmp &= ~(1 << gpio);
1654 OUTL(tmp, base + 0x48);
1655 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001656
1657 return 0;
1658}
1659
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001660/*
1661 * Suited for:
1662 * - abit IP35: Intel P35 + ICH9R
1663 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001664 * - ASUS P5LD2
Dima Veselov9d8f53d2014-07-14 18:04:15 +00001665 * - ASUS P5LD2-MQ
Idwer Vollering4d0cde12012-09-07 08:27:46 +00001666 * - ASUS P5LD2-VM
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001667 * - ASUS P5LD2-VM DH
Uwe Hermann93f66db2008-05-22 21:19:38 +00001668 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001669static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001670{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001671 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001672}
1673
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001674/*
1675 * Suited for:
1676 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001677 */
1678static int intel_ich_gpio18_raise(void)
1679{
1680 return intel_ich_gpio_set(18, 1);
1681}
1682
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001683/*
1684 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001685 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001686 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001687static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001688{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001689 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001690}
1691
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001692/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001693 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001694 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
1695 */
1696static int intel_ich_gpio20_raise(void)
1697{
1698 return intel_ich_gpio_set(20, 1);
1699}
1700
1701/*
1702 * Suited for:
Stefan Taunereb582572012-09-21 12:52:50 +00001703 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001704 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1705 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001706 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001707 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001708 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Stefan Taunereb582572012-09-21 12:52:50 +00001709 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001710 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001711 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001712 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001713 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001714 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001715 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001716 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001717static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001718{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001719 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001720}
1721
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001722/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001723 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001724 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001725 * - ASUS P4B533-E: socket478 + 845E + ICH4
1726 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001727 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001728 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001729static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001730{
1731 return intel_ich_gpio_set(22, 1);
1732}
1733
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001734/*
1735 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001736 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001737 * - ASUS P5LP-LE used in ...
1738 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1739 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001740 */
1741static int intel_ich_gpio34_raise(void)
1742{
1743 return intel_ich_gpio_set(34, 1);
1744}
1745
1746/*
1747 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001748 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001749 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001750 */
1751static int intel_ich_gpio38_raise(void)
1752{
1753 return intel_ich_gpio_set(38, 1);
1754}
1755
1756/*
1757 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001758 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1759 */
1760static int intel_ich_gpio43_raise(void)
1761{
1762 return intel_ich_gpio_set(43, 1);
1763}
1764
1765/*
1766 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001767 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001768 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001769static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001770{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001771 int ret;
1772 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1773 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001774 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001775 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001776 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1777 return ret;
1778}
1779
1780/*
1781 * Suited for:
1782 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1783 */
1784static int board_hp_p2706t(void)
1785{
1786 int ret;
1787 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1788 if (!ret)
1789 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001790 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001791}
1792
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001793/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001794 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001795 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1796 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1797 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001798 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001799 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001800static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001801{
1802 return intel_ich_gpio_set(23, 1);
1803}
1804
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001805/*
1806 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001807 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001808 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001809 */
1810static int intel_ich_gpio25_raise(void)
1811{
1812 return intel_ich_gpio_set(25, 1);
1813}
1814
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001815/*
1816 * Suited for:
1817 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001818 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001819static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001820{
1821 return intel_ich_gpio_set(26, 1);
1822}
1823
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001824/*
1825 * Suited for:
Stefan Tauner98546c92012-11-05 12:20:29 +00001826 * - ASUS DSAN-DX
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001827 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001828 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001829 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001830 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001831 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001832static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001833{
1834 return intel_ich_gpio_set(32, 1);
1835}
1836
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001837/*
1838 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001839 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1840 */
1841static int board_aopen_i975xa_ydg(void)
1842{
1843 int ret;
1844
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001845 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001846 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001847 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1848 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001849 */
1850/*
1851 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1852 if (!ret)
1853*/
1854 ret = intel_ich_gpio_set(33, 1);
1855
1856 return ret;
1857}
1858
1859/*
1860 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001861 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001862 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001863static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001864{
1865 int ret;
1866
1867 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1868 ret = intel_ich_gpio_set(22, 1);
1869 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1870 ret = intel_ich_gpio_set(23, 1);
1871
1872 return ret;
1873}
1874
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001875/*
1876 * Suited for:
1877 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001878 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001879static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001880{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001881 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001882
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001883 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1884 if (!ret)
1885 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001886
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001887 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001888}
1889
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001890/*
1891 * Suited for:
1892 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001893 */
Michael Karcher06477332010-03-19 22:49:09 +00001894static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001895{
Michael Karcher06477332010-03-19 22:49:09 +00001896 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001897 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001898
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001899 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001900 dev = pci_dev_find(0x1106, 0x3057);
1901 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001902 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001903 return -1;
1904 }
1905
Sean Nelson316a29f2010-05-07 20:09:04 +00001906 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001907 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +00001908
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001909 /* Select GPO function on multiplexed pins. */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001910 tmp = pci_read_byte(dev, 0x54);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001911 switch (gpio) {
1912 case 0:
1913 tmp &= ~0x03;
1914 break;
1915 case 1:
1916 tmp |= 0x04;
1917 break;
1918 case 2:
1919 tmp |= 0x08;
1920 break;
1921 case 3:
1922 tmp |= 0x10;
1923 break;
Michael Karcher06477332010-03-19 22:49:09 +00001924 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001925 pci_write_byte(dev, 0x54, tmp);
1926
1927 /* PM IO base */
1928 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1929
1930 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001931 tmp = INL(base + 0x4C);
1932 if (raise)
1933 tmp |= 1U << gpio;
1934 else
1935 tmp &= ~(1U << gpio);
1936 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001937
1938 return 0;
1939}
1940
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001941/*
1942 * Suited for:
1943 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001944 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001945 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001946static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001947{
1948 return via_apollo_gpo_set(4, 0);
1949}
1950
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001951/*
1952 * Suited for:
1953 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001954 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001955static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001956{
1957 return via_apollo_gpo_set(0, 0);
1958}
1959
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001960/*
Michael Karchera08d0f22011-07-25 17:25:24 +00001961 * Enable some GPIO pin on SiS southbridge and enables SIO flash writes.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001962 *
1963 * Suited for: