blob: 3437792883cfe4a2d3f4beaebdf669ec95aced14 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Nico Huber93c30692017-03-20 14:25:09 +010010 * Copyright (C) 2017 secunet Security Networks AG
11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
Ollie Lho184a4042005-11-26 21:55:36 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 */
26
27/*
28 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000029 */
30
Lane Brooksd54958a2007-11-13 16:45:22 +000031#define _LARGEFILE64_SOURCE
32
Ollie Lhocbbf1252004-03-17 22:22:08 +000033#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000034#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000035#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000036#include <inttypes.h>
37#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000038#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000039#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000040#include "hwaccess.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000041
Michael Karcher89bed6d2010-06-13 10:16:12 +000042#define NOT_DONE_YET 1
43
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000044#if defined(__i386__) || defined(__x86_64__)
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000047{
48 uint8_t tmp;
49
Uwe Hermann372eeb52007-12-04 21:49:06 +000050 /*
51 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
52 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
53 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000054 tmp = pci_read_byte(dev, 0x47);
55 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000056 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000057
58 return 0;
59}
60
Rudolf Marek23907d82012-02-07 21:29:48 +000061static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
62{
63 uint8_t tmp;
64
65 /* enable ROMCS for writes */
66 tmp = pci_read_byte(dev, 0x43);
67 tmp |= 0x80;
68 pci_write_byte(dev, 0x43, tmp);
69
70 /* read the bootstrapping register */
71 tmp = pci_read_byte(dev, 0x40) & 0x3;
72 switch (tmp) {
73 case 3:
74 internal_buses_supported = BUS_FWH;
75 break;
76 case 2:
77 internal_buses_supported = BUS_LPC;
78 break;
79 default:
80 internal_buses_supported = BUS_PARALLEL;
81 break;
82 }
83
84 return 0;
85}
86
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000087static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
88{
89 uint8_t tmp;
90
91 tmp = pci_read_byte(dev, 0xd0);
92 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000093 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000094
95 return 0;
96}
97
98static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
99{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000100 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000101 uint8_t new, newer;
102
103 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
104 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000105 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000106 new &= (~0x04); /* No idea why we clear bit 2. */
107 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000108 rpci_write_byte(dev, SIS_MAPREG, new);
109 newer = pci_read_byte(dev, SIS_MAPREG);
110 if (newer != new) { /* FIXME: share this with other code? */
111 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
112 SIS_MAPREG, new, name);
113 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000114 return -1;
115 }
116 return 0;
117}
118
119static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
120{
121 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000122
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000123 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
124 if (!sbdev)
125 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
126 if (!sbdev)
127 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
128 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000129 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000130 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000131 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000132 sbdev->vendor_id, sbdev->device_id,
133 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000134 return sbdev;
135}
136
137static int enable_flash_sis501(struct pci_dev *dev, const char *name)
138{
139 uint8_t tmp;
140 int ret = 0;
141 struct pci_dev *sbdev;
142
143 sbdev = find_southbridge(dev->vendor_id, name);
144 if (!sbdev)
145 return -1;
146
147 ret = enable_flash_sis_mapping(sbdev, name);
148
149 tmp = sio_read(0x22, 0x80);
150 tmp &= (~0x20);
151 tmp |= 0x4;
152 sio_write(0x22, 0x80, tmp);
153
154 tmp = sio_read(0x22, 0x70);
155 tmp &= (~0x20);
156 tmp |= 0x4;
157 sio_write(0x22, 0x70, tmp);
158
159 return ret;
160}
161
162static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
163{
164 uint8_t tmp;
165 int ret = 0;
166 struct pci_dev *sbdev;
167
168 sbdev = find_southbridge(dev->vendor_id, name);
169 if (!sbdev)
170 return -1;
171
172 ret = enable_flash_sis_mapping(sbdev, name);
173
174 tmp = sio_read(0x22, 0x50);
175 tmp &= (~0x20);
176 tmp |= 0x4;
177 sio_write(0x22, 0x50, tmp);
178
179 return ret;
180}
181
Stefan Taunere34e3e82013-01-01 00:06:51 +0000182static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000183{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000184 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000185 uint8_t new, newer;
186 int ret = 0;
187 struct pci_dev *sbdev;
188
189 sbdev = find_southbridge(dev->vendor_id, name);
190 if (!sbdev)
191 return -1;
192
193 ret = enable_flash_sis_mapping(sbdev, name);
194
Stefan Taunere34e3e82013-01-01 00:06:51 +0000195 new = pci_read_byte(sbdev, SIS_REG);
196 new &= (~dis_mask);
197 new |= en_mask;
198 rpci_write_byte(sbdev, SIS_REG, new);
199 newer = pci_read_byte(sbdev, SIS_REG);
200 if (newer != new) { /* FIXME: share this with other code? */
201 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
202 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000203 ret = -1;
204 }
205
206 return ret;
207}
208
Stefan Taunere34e3e82013-01-01 00:06:51 +0000209static int enable_flash_sis530(struct pci_dev *dev, const char *name)
210{
211 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
212}
213
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000214static int enable_flash_sis540(struct pci_dev *dev, const char *name)
215{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000216 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000217}
218
Uwe Hermann987942d2006-11-07 11:16:21 +0000219/* Datasheet:
220 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
221 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
222 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
223 * - Order Number: 290562-001
224 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000225static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000226{
227 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000228 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000229
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000230 internal_buses_supported = BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000231
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000232 old = pci_read_word(dev, xbcs);
233
234 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000235 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000236 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000237 * Set bit 7: Extended BIOS Enable (PCI master accesses to
238 * FFF80000-FFFDFFFF are forwarded to ISA).
239 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
240 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
241 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
242 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
243 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
244 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
245 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000246 if (dev->device_id == 0x122e || dev->device_id == 0x7000
247 || dev->device_id == 0x1234)
248 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000249 else
250 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000251
252 if (new == old)
253 return 0;
254
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000255 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000256
Stefan Taunere34e3e82013-01-01 00:06:51 +0000257 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
258 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000259 return -1;
260 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000261
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000262 return 0;
263}
264
Duncan Laurie4095ed72014-08-20 15:39:32 +0000265/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
266 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
267 *
268 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000269 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000270static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
271 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000272{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000273 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000274
Stefan Tauner92d6a862013-10-25 00:33:37 +0000275 switch (ich_generation) {
276 case CHIPSET_ICH_UNKNOWN:
277 return ERROR_FATAL;
278 /* Non-SPI-capable */
279 case CHIPSET_ICH:
280 case CHIPSET_ICH2345:
281 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000282 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
283 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000284 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
285 * mentions that the prefetching and caching does only happen for direct memory reads.
286 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
287 * programmed access only and not memory mapping. */
288 case CHIPSET_TUNNEL_CREEK:
289 case CHIPSET_POULSBO:
290 case CHIPSET_CENTERTON:
291 old = pci_read_byte(dev, bios_cntl + 1);
292 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
293 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000294 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000295 case CHIPSET_ICH7:
296 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000297 if (ich_generation == CHIPSET_BAYTRAIL)
298 old = (mmio_readl(addr) >> 2) & 0x3;
299 else
300 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000301 msg_pdbg("SPI Read Configuration: ");
302 if (old == 3)
303 msg_pdbg("invalid prefetching/caching settings, ");
304 else
305 msg_pdbg("prefetching %sabled, caching %sabled, ",
306 (old & 0x2) ? "en" : "dis",
307 (old & 0x1) ? "dis" : "en");
308 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000309
Duncan Laurie4095ed72014-08-20 15:39:32 +0000310 if (ich_generation == CHIPSET_BAYTRAIL)
311 wanted = old = mmio_readl(addr);
312 else
313 wanted = old = pci_read_byte(dev, bios_cntl);
314
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000315 /*
316 * Quote from the 6 Series datasheet (Document Number: 324645-004):
317 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
318 * 1 = BIOS region SMM protection is enabled.
319 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000320 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000321 *
322 * Try to unset it in any case.
323 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000324 *
325 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
326 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000327 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000328 int smm_bwp_bit;
329 if (ich_generation == CHIPSET_CENTERTON)
330 smm_bwp_bit = 7;
331 else
332 smm_bwp_bit = 5;
333 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000334
Stefan Tauner92d6a862013-10-25 00:33:37 +0000335 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
336 if (ich_generation == CHIPSET_TUNNEL_CREEK)
337 wanted |= (1 << 2);
338
339 wanted |= (1 << 0); /* Set BIOS Write Enable */
340 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000341
342 /* Only write the register if it's necessary */
343 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000344 if (ich_generation == CHIPSET_BAYTRAIL) {
345 rmmio_writel(wanted, addr);
346 new = mmio_readl(addr);
347 } else {
348 rpci_write_byte(dev, bios_cntl, wanted);
349 new = pci_read_byte(dev, bios_cntl);
350 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000351 } else
352 new = old;
353
354 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
355 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
356 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000357 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000358 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000359
Stefan Reinauer62218c32012-08-26 02:35:13 +0000360 if (new != wanted)
Stefan Tauner92d6a862013-10-25 00:33:37 +0000361 msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n"
362 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000363
Stefan Tauner92d6a862013-10-25 00:33:37 +0000364 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000365 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000366 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000367
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000368 return 0;
369}
370
Duncan Laurie4095ed72014-08-20 15:39:32 +0000371static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
372 uint8_t bios_cntl)
373{
374 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
375}
376
377static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
378{
379 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
380}
381
Stefan Tauner92d6a862013-10-25 00:33:37 +0000382static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000383{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000384 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
385 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000386 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000387 switch (ich_generation) {
388 case CHIPSET_ICH:
389 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
390 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
391 break;
392 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000393 fwh_sel1 = 0xe8;
394 fwh_sel2 = 0xee;
395 fwh_dec_en_lo = 0xf0;
396 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000397 implemented = 1;
398 break;
399 case CHIPSET_POULSBO:
400 case CHIPSET_TUNNEL_CREEK:
401 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
402 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
403 break;
404 case CHIPSET_CENTERTON:
405 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
406 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000407 case CHIPSET_BAYTRAIL: {
408 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
409 if (ilb_base == 0) {
410 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
411 return ERROR_FATAL;
412 }
413 ilb = rphysmap("BYT IBASE", ilb_base, 512);
414 fwh_sel1 = 0x18;
415 fwh_dec_en_lo = 0xd8;
416 fwh_dec_en_hi = 0xd9;
417 implemented = 1;
418 break;
419 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000420 case CHIPSET_ICH6:
421 case CHIPSET_ICH7:
422 default: /* Future version might behave the same */
423 fwh_sel1 = 0xd0;
424 fwh_sel2 = 0xd4;
425 fwh_dec_en_lo = 0xd8;
426 fwh_dec_en_hi = 0xd9;
427 implemented = 1;
428 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000429 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000430
Stefan Tauner92d6a862013-10-25 00:33:37 +0000431 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000432 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000433 if (!implemented) {
434 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
435 goto idsel_garbage_out;
436 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000437 errno = 0;
438 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000439 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000440 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000441 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000442 goto idsel_garbage_out;
443 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000444 uint64_t fwh_mask = 0xffffffff;
445 if (fwh_sel2 > 0)
446 fwh_mask |= (0xffffULL << 32);
447 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000448 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000449 goto idsel_garbage_out;
450 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000451 uint64_t fwh_idsel_old;
452 if (ich_generation == CHIPSET_BAYTRAIL) {
453 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
454 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
455 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000456 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000457 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
458 if (fwh_sel2 > 0) {
459 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
460 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
461 }
462 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000463 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000464 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000465 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000466 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000467 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000468idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000469 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000470 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000471 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000472 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000473
Stefan Tauner92d6a862013-10-25 00:33:37 +0000474 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000475 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000476 return 0;
477 }
478
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000479 /* Ignore all legacy ranges below 1 MB.
480 * We currently only support flashing the chip which responds to
481 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
482 * have to be adjusted.
483 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000484 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
485 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000486 uint32_t fwh_conf;
487 if (ich_generation == CHIPSET_BAYTRAIL)
488 fwh_conf = mmio_readl(ilb + fwh_sel1);
489 else
490 fwh_conf = pci_read_long(dev, fwh_sel1);
491
Stefan Tauner92d6a862013-10-25 00:33:37 +0000492 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000493 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000494 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000495 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000496 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000497 (0x1ff8 + i) * 0x80000,
498 (0x1ff0 + i) * 0x80000,
499 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000500 if ((tmp == 0) && contiguous) {
501 max_decode_fwh_idsel = (8 - i) * 0x80000;
502 } else {
503 contiguous = 0;
504 }
505 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000506 if (fwh_sel2 > 0) {
507 /* FWH_SEL2 */
508 fwh_conf = pci_read_word(dev, fwh_sel2);
509 for (i = 3; i >= 0; i--) {
510 int tmp = (fwh_conf >> (i * 4)) & 0xf;
511 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
512 (0xff4 + i) * 0x100000,
513 (0xff0 + i) * 0x100000,
514 tmp);
515 if ((tmp == 0) && contiguous) {
516 max_decode_fwh_idsel = (8 - i) * 0x100000;
517 } else {
518 contiguous = 0;
519 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000520 }
521 }
522 contiguous = 1;
523 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000524 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
525 fwh_conf <<= 8;
526 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000527 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000528 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000529 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000530 (0x1ff8 + i) * 0x80000,
531 (0x1ff0 + i) * 0x80000,
532 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000533 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000534 max_decode_fwh_decode = (8 - i) * 0x80000;
535 } else {
536 contiguous = 0;
537 }
538 }
539 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000540 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000541 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000542 (0xff4 + i) * 0x100000,
543 (0xff0 + i) * 0x100000,
544 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000545 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000546 max_decode_fwh_decode = (8 - i) * 0x100000;
547 } else {
548 contiguous = 0;
549 }
550 }
551 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000552 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000553
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000554 return 0;
555}
556
Stefan Tauner92d6a862013-10-25 00:33:37 +0000557static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000558{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000559 int err;
560
561 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000562 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000563 return err;
564
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000565 internal_buses_supported = BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000566 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000567}
568
Stefan Tauner92d6a862013-10-25 00:33:37 +0000569static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000570{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000571 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000572}
573
Stefan Tauner92d6a862013-10-25 00:33:37 +0000574static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000575{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000576 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000577}
578
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000579static int enable_flash_ich6(struct pci_dev *dev, const char *name)
580{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000581 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000582}
583
Adam Jurkowskie4984102009-12-21 15:30:46 +0000584static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
585{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000586 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000587}
588
Nico Huber0ea99f52017-03-17 17:22:53 +0100589static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ich_chipset ich_generation,
590 const uint8_t *const rcrb)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000591{
Nico Huber0ea99f52017-03-17 17:22:53 +0100592 uint32_t gcs;
Nico Huber93c30692017-03-20 14:25:09 +0100593 const char *reg_name;
594 bool bild, top_swap;
Nico Huber0ea99f52017-03-17 17:22:53 +0100595
596 switch (ich_generation) {
597 case CHIPSET_BAYTRAIL:
Nico Huber93c30692017-03-20 14:25:09 +0100598 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100599 gcs = mmio_readl(rcrb + 0);
Nico Huber93c30692017-03-20 14:25:09 +0100600 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100601 top_swap = (gcs & 2) >> 1;
602 break;
Nico Huber93c30692017-03-20 14:25:09 +0100603 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700604 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber93c30692017-03-20 14:25:09 +0100605 reg_name = "BIOS_SPI_BC";
606 gcs = pci_read_long(dev, 0xdc);
607 bild = (gcs >> 7) & 1;
608 top_swap = (gcs >> 4) & 1;
609 break;
Nico Huber0ea99f52017-03-17 17:22:53 +0100610 default:
Nico Huber93c30692017-03-20 14:25:09 +0100611 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100612 gcs = mmio_readl(rcrb + 0x3410);
Nico Huber93c30692017-03-20 14:25:09 +0100613 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100614 top_swap = mmio_readb(rcrb + 0x3414) & 1;
615 break;
616 }
617
Nico Huber93c30692017-03-20 14:25:09 +0100618 msg_pdbg("%s = 0x%x: ", reg_name, gcs);
619 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
Duncan Laurie4095ed72014-08-20 15:39:32 +0000620
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000621 static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
622 static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000623 static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000624 static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000625 static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
Duncan Laurie823096e2014-08-20 15:39:38 +0000626 static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000627 static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000628 static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
629
Stefan Tauner92d6a862013-10-25 00:33:37 +0000630 const char *const *straps_names;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000631 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000632 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000633 /* EP80579 may need further changes, but this is the least
634 * intrusive way to get correct BOOT Strap printing without
635 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000636 if (dev->device_id == 0x5031)
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000637 straps_names = straps_names_EP80579;
638 else
639 straps_names = straps_names_ich7_nm10;
640 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000641 case CHIPSET_ICH8:
642 case CHIPSET_ICH9:
643 case CHIPSET_ICH10:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000644 straps_names = straps_names_ich8910;
645 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000646 case CHIPSET_TUNNEL_CREEK:
647 straps_names = straps_names_tunnel_creek;
648 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000649 case CHIPSET_5_SERIES_IBEX_PEAK:
650 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000651 case CHIPSET_7_SERIES_PANTHER_POINT:
652 straps_names = straps_names_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000653 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000654 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000655 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000656 case CHIPSET_BAYTRAIL:
Duncan Laurie823096e2014-08-20 15:39:38 +0000657 straps_names = straps_names_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000658 break;
659 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100660 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huber93c30692017-03-20 14:25:09 +0100661 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700662 case CHIPSET_C620_SERIES_LEWISBURG:
Duncan Laurie90eb2262013-03-15 03:12:29 +0000663 straps_names = straps_names_pch8_lp;
664 break;
665 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000666 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Duncan Laurie90eb2262013-03-15 03:12:29 +0000667 straps_names = straps_names_unknown;
668 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000669 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000670 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000671 straps_names = straps_names_unknown;
672 break;
673 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000674
Duncan Laurie4095ed72014-08-20 15:39:32 +0000675 uint8_t bbs;
676 switch (ich_generation) {
677 case CHIPSET_TUNNEL_CREEK:
678 bbs = (gcs >> 1) & 0x1;
679 break;
680 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100681 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
682 /* LP PCHs use a single bit for BBS */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000683 bbs = (gcs >> 10) & 0x1;
684 break;
Nico Huber93c30692017-03-20 14:25:09 +0100685 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700686 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber93c30692017-03-20 14:25:09 +0100687 bbs = (gcs >> 6) & 0x1;
688 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000689 default:
690 /* Other chipsets use two bits for BBS */
691 bbs = (gcs >> 10) & 0x3;
692 break;
693 }
694 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
695
696 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
697 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
698 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
699}
700
701static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
702{
703
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000704 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000705 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
706 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000707
708 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000709 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000710 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000711 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000712
Nico Huber0ea99f52017-03-17 17:22:53 +0100713 enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000714
Stefan Tauner92d6a862013-10-25 00:33:37 +0000715 /* Handle FWH-related parameters and initialization */
716 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
717 if (ret_fwh == ERROR_FATAL)
718 return ret_fwh;
719
720 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
721 uint16_t spibar_offset;
722 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000723 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000724 case CHIPSET_ICH_UNKNOWN:
725 return ERROR_FATAL;
726 case CHIPSET_ICH7:
727 case CHIPSET_ICH8:
728 case CHIPSET_TUNNEL_CREEK:
729 case CHIPSET_CENTERTON:
730 spibar_offset = 0x3020;
731 break;
732 case CHIPSET_ICH9:
733 default: /* Future version might behave the same */
734 spibar_offset = 0x3800;
735 break;
736 }
737 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
738 void *spibar = rcrb + spibar_offset;
739
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000740 /* This adds BUS_SPI */
Nico Huber560111e2017-04-26 12:27:17 +0200741 int ret_spi = ich_init_spi(spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000742 if (ret_spi == ERROR_FATAL)
743 return ret_spi;
744
Stefan Tauner92d6a862013-10-25 00:33:37 +0000745 if (ret_fwh || ret_spi)
746 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000747
Stefan Tauner92d6a862013-10-25 00:33:37 +0000748 return 0;
749}
750
751static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
752{
753 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
754}
755
756static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
757{
758 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000759}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000760
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000761static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000762{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000763 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000764}
765
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000766static int enable_flash_ich8(struct pci_dev *dev, const char *name)
767{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000768 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000769}
770
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000771static int enable_flash_ich9(struct pci_dev *dev, const char *name)
772{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000773 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000774}
775
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000776static int enable_flash_ich10(struct pci_dev *dev, const char *name)
777{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000778 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000779}
780
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000781/* Ibex Peak aka. 5 series & 3400 series */
782static int enable_flash_pch5(struct pci_dev *dev, const char *name)
783{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000784 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000785}
786
787/* Cougar Point aka. 6 series & c200 series */
788static int enable_flash_pch6(struct pci_dev *dev, const char *name)
789{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000790 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000791}
792
Stefan Tauner2abab942012-04-27 20:41:23 +0000793/* Panther Point aka. 7 series */
794static int enable_flash_pch7(struct pci_dev *dev, const char *name)
795{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000796 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000797}
798
799/* Lynx Point aka. 8 series */
800static int enable_flash_pch8(struct pci_dev *dev, const char *name)
801{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000802 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000803}
804
Stefan Tauner92d6a862013-10-25 00:33:37 +0000805/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000806static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
807{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000808 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000809}
810
811/* Wellsburg (for Haswell-EP Xeons) */
812static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
813{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000814 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000815}
816
Duncan Laurie823096e2014-08-20 15:39:38 +0000817/* Wildcat Point */
818static int enable_flash_pch9(struct pci_dev *dev, const char *name)
819{
820 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
821}
822
Nico Huber51205912017-03-17 17:59:54 +0100823/* Wildcat Point LP */
824static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
825{
826 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
827}
828
Nico Huber93c30692017-03-20 14:25:09 +0100829/* Sunrise Point */
830static int enable_flash_pch100_shutdown(void *const pci_acc)
831{
832 pci_cleanup(pci_acc);
833 return 0;
834}
835
David Hendricksa5216362017-08-08 20:02:22 -0700836static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation)
Nico Huber93c30692017-03-20 14:25:09 +0100837{
Nico Huber93c30692017-03-20 14:25:09 +0100838 int ret = ERROR_FATAL;
839
840 /*
841 * The SPI PCI device is usually hidden (by hiding PCI vendor
842 * and device IDs). So we need a PCI access method that works
843 * even when the OS doesn't know the PCI device. We can't use
844 * this method globally since it would bring along other con-
845 * straints (e.g. on PCI domains, extended PCIe config space).
846 */
847 struct pci_access *const pci_acc = pci_alloc();
Youness Alaouia54ceb12017-07-26 18:03:36 -0400848 struct pci_access *const saved_pacc = pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100849 if (!pci_acc) {
850 msg_perr("Can't allocate PCI accessor.\n");
851 return ret;
852 }
853 pci_acc->method = PCI_ACCESS_I386_TYPE1;
854 pci_init(pci_acc);
855 register_shutdown(enable_flash_pch100_shutdown, pci_acc);
856
857 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5);
858 if (!spi_dev) {
859 msg_perr("Can't allocate PCI device.\n");
860 return ret;
861 }
862
Youness Alaouia54ceb12017-07-26 18:03:36 -0400863 /* Modify pacc so the rpci_write can register the undo callback with a
864 * device using the correct pci_access */
865 pacc = pci_acc;
Nico Huber93c30692017-03-20 14:25:09 +0100866 enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
867
868 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
869 if (ret_bc == ERROR_FATAL)
870 goto _freepci_ret;
871
872 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
873 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
874 if (spibar == ERROR_PTR)
875 goto _freepci_ret;
876 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
877
878 /* This adds BUS_SPI */
879 const int ret_spi = ich_init_spi(spibar, pch_generation);
880 if (ret_spi != ERROR_FATAL) {
881 if (ret_bc || ret_spi)
882 ret = ERROR_NONFATAL;
883 else
884 ret = 0;
885 }
886
887_freepci_ret:
888 pci_free_dev(spi_dev);
Youness Alaouia54ceb12017-07-26 18:03:36 -0400889 pacc = saved_pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100890 return ret;
891}
892
David Hendricksa5216362017-08-08 20:02:22 -0700893static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
894{
895 return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT);
896}
897
898static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
899{
900 return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG);
901}
902
Duncan Laurie4095ed72014-08-20 15:39:32 +0000903/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
904 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
905 *
906 * Differences include:
907 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
908 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
909 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
910 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
911 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
912 */
913static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
914{
915 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
916
917 /* Get physical address of Root Complex Register Block */
918 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
919 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
920
921 /* Handle GCS (in RCRB) */
922 void *rcrb = physmap("BYT RCRB", rcba, 4);
Nico Huber0ea99f52017-03-17 17:22:53 +0100923 enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000924 physunmap(rcrb, 4);
925
926 /* Handle fwh_idsel parameter */
927 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
928 if (ret_fwh == ERROR_FATAL)
929 return ret_fwh;
930
931 internal_buses_supported = BUS_FWH;
932
933 /* Get physical address of SPI Base Address and map it */
934 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
935 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
936 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
937
938 /* Enable Flash Writes.
939 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
940 */
941 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
942
Nico Huber560111e2017-04-26 12:27:17 +0200943 int ret_spi = ich_init_spi(spibar, ich_generation);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000944 if (ret_spi == ERROR_FATAL)
945 return ret_spi;
946
947 if (ret_fwh || ret_spi)
948 return ERROR_NONFATAL;
949
950 return 0;
951}
952
Michael Karcher89bed6d2010-06-13 10:16:12 +0000953static int via_no_byte_merge(struct pci_dev *dev, const char *name)
954{
955 uint8_t val;
956
957 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000958 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +0000959 msg_pdbg("Disabling byte merging\n");
960 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000961 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000962 }
963 return NOT_DONE_YET; /* need to find south bridge, too */
964}
965
Uwe Hermann372eeb52007-12-04 21:49:06 +0000966static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000967{
Ollie Lho184a4042005-11-26 21:55:36 +0000968 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000969
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000970 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000971 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000972
Uwe Hermannffec5f32007-08-23 16:08:21 +0000973 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000974 val = pci_read_byte(dev, 0x40);
975 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000976 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000977
978 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000979 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000980 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000981 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000982
Helge Wagnerdd73d832012-08-24 23:03:46 +0000983 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000984 /* All memory cycles, not just ROM ones, go to LPC. */
985 val = pci_read_byte(dev, 0x59);
986 val &= ~0x80;
987 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000988 }
989
Uwe Hermanna7e05482007-05-09 10:17:44 +0000990 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000991}
992
Helge Wagnerdd73d832012-08-24 23:03:46 +0000993static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
994{
995 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
996 if (south_north == NULL) {
997 msg_perr("Could not find South-North Module Interface Control device!\n");
998 return ERROR_FATAL;
999 }
1000
1001 msg_pdbg("Strapped to ");
1002 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
1003 msg_pdbg("LPC.\n");
1004 return enable_flash_vt823x(dev, name);
1005 }
1006 msg_pdbg("SPI.\n");
1007
1008 uint32_t mmio_base;
1009 void *mmio_base_physmapped;
1010 uint32_t spi_cntl;
1011 #define SPI_CNTL_LEN 0x08
1012 uint32_t spi0_mm_base = 0;
1013 switch(dev->device_id) {
1014 case 0x8353: /* VX800/VX820 */
1015 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
1016 break;
1017 case 0x8409: /* VX855/VX875 */
1018 case 0x8410: /* VX900 */
1019 mmio_base = pci_read_long(dev, 0xbc) << 8;
1020 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001021 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +00001022 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001023
1024 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
1025 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
1026 if ((spi_cntl & 0x01) == 0) {
1027 msg_pdbg ("SPI Bus0 disabled!\n");
1028 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1029 return ERROR_FATAL;
1030 }
1031 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
1032 spi0_mm_base = spi_cntl & 0xFFFFFF00;
1033
1034 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
1035 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
1036 if ((spi_cntl & 0x01) == 1)
1037 msg_pdbg2("SPI Bus1 is enabled too.\n");
1038
1039 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1040 break;
1041 default:
1042 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
1043 return ERROR_FATAL;
1044 }
1045
Nico Huber560111e2017-04-26 12:27:17 +02001046 return via_init_spi(spi0_mm_base);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001047}
1048
1049static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
1050{
Nico Huber560111e2017-04-26 12:27:17 +02001051 return via_init_spi(pci_read_long(dev, 0xbc) << 8);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001052}
1053
Uwe Hermann372eeb52007-12-04 21:49:06 +00001054static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001055{
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001056 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001057
Uwe Hermann394131e2008-10-18 21:14:13 +00001058#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
1059#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001060#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
1061#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001062
Uwe Hermann394131e2008-10-18 21:14:13 +00001063#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
1064#define ROM_WRITE_ENABLE (1 << 1)
1065#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
1066#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001067#define CS5530_ISA_MASTER (1 << 7)
1068#define CS5530_ENABLE_SA2320 (1 << 2)
1069#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001070
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001071 internal_buses_supported = BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001072 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
1073 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001074 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
1075 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001076 * Make the configured ROM areas writable.
1077 */
1078 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
1079 reg8 |= LOWER_ROM_ADDRESS_RANGE;
1080 reg8 |= UPPER_ROM_ADDRESS_RANGE;
1081 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001082 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001083
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001084 /* Set positive decode on ROM. */
1085 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
1086 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001087 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001088
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001089 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
1090 if (reg8 & CS5530_ISA_MASTER) {
1091 /* We have A0-A23 available. */
1092 max_rom_decode.parallel = 16 * 1024 * 1024;
1093 } else {
1094 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
1095 if (reg8 & CS5530_ENABLE_SA2320) {
1096 /* We have A0-19, A20-A23 available. */
1097 max_rom_decode.parallel = 16 * 1024 * 1024;
1098 } else if (reg8 & CS5530_ENABLE_SA20) {
1099 /* We have A0-19, A20 available. */
1100 max_rom_decode.parallel = 2 * 1024 * 1024;
1101 } else {
1102 /* A20 and above are not active. */
1103 max_rom_decode.parallel = 1024 * 1024;
1104 }
1105 }
1106
Ollie Lhocbbf1252004-03-17 22:22:08 +00001107 return 0;
1108}
1109
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001110/*
Mart Raudseppe1344da2008-02-08 10:10:57 +00001111 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001112 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +00001113 *
1114 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
1115 * To enable write to NOR Boot flash for the benefit of systems that have such
1116 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001117 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001118static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001119{
Uwe Hermann394131e2008-10-18 21:14:13 +00001120#define MSR_RCONF_DEFAULT 0x1808
1121#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001122
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001123 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001124
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001125 /* Geode only has a single core */
1126 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001127 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001128
1129 msr = rdmsr(MSR_RCONF_DEFAULT);
1130 if ((msr.hi >> 24) != 0x22) {
1131 msr.hi &= 0xfbffffff;
1132 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001133 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001134
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001135 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001136 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001137 msr.lo |= 0x08;
1138 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001139
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001140 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001141
Uwe Hermann394131e2008-10-18 21:14:13 +00001142#undef MSR_RCONF_DEFAULT
1143#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001144 return 0;
1145}
1146
Uwe Hermann372eeb52007-12-04 21:49:06 +00001147static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001148{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001149 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001150 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001151
Stefan Taunere34e3e82013-01-01 00:06:51 +00001152 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001153
Stefan Taunere34e3e82013-01-01 00:06:51 +00001154 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001155
Stefan Taunere34e3e82013-01-01 00:06:51 +00001156 if (new != 0xee) { /* FIXME: share this with other code? */
1157 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001158 return -1;
1159 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001160
Ollie Lhocbbf1252004-03-17 22:22:08 +00001161 return 0;
1162}
1163
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001164/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1165 *
1166 * ROM decode control register matrix
1167 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
1168 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1169 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1170 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1171 */
1172static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001173{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001174 #define AMD_MAPREG 0x43
1175 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001176 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001177
Stefan Taunere34e3e82013-01-01 00:06:51 +00001178 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001179 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001180 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001181 rpci_write_byte(dev, AMD_MAPREG, new);
1182 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001183 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001184 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001185 } else
1186 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001187 }
1188
Uwe Hermann190f8492008-10-25 18:03:50 +00001189 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001190 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001191 new = old | 0x01;
1192 if (new == old)
1193 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001194 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001195
Stefan Taunere34e3e82013-01-01 00:06:51 +00001196 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001197 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001198 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001199 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001200 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001201 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001202
Ollie Lhocbbf1252004-03-17 22:22:08 +00001203 return 0;
1204}
1205
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001206static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1207{
1208 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1209 max_rom_decode.lpc = 5 * 1024 * 1024;
1210 return enable_flash_amd_via(dev, name, 0xC0);
1211}
1212
1213static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1214{
1215 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1216 max_rom_decode.parallel = 512 * 1024;
1217 return enable_flash_amd_via(dev, name, 0xC0);
1218}
1219
1220/* Works for VT82C686A/B too. */
1221static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1222{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001223 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001224 max_rom_decode.parallel = 1024 * 1024;
1225 return enable_flash_amd_via(dev, name, 0xE0);
1226}
1227
Marc Jones3af487d2008-10-15 17:50:29 +00001228static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1229{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001230 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001231 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001232 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001233
Jason Wanga3f04be2008-11-28 21:36:51 +00001234 /* Clear ROM protect 0-3. */
1235 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001236 prot = pci_read_long(dev, reg);
1237 /* No protection flags for this region?*/
1238 if ((prot & 0x3) == 0)
1239 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001240 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001241 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001242 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001243 (prot & 0xfffff800),
1244 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001245 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001246 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001247 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001248 if ((prot & 0x3) != 0) {
1249 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001250 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001251 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001252 (prot & 0xfffff800),
1253 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001254 continue;
1255 }
1256 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001257 }
1258
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001259 internal_buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001260
1261 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001262
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001263 /* Read ROM strap override register. */
1264 OUTB(0x8f, 0xcd6);
1265 reg = INB(0xcd7);
1266 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001267 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001268 if (reg & 0x02) {
1269 switch ((reg & 0x0c) >> 2) {
1270 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001271 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001272 break;
1273 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001274 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001275 break;
1276 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001277 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001278 break;
1279 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001280 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001281 break;
1282 }
1283 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001284 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001285
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001286 /* Force enable SPI ROM in SB600 PM register.
1287 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001288 * But how can we know which ROM we are going to handle? So we have
1289 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001290 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1291 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001292 */
1293 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001294 OUTB(0x8f, 0xcd6);
1295 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001296 */
Marc Jones3af487d2008-10-15 17:50:29 +00001297
Michael Karcherb05b9e12010-07-22 18:04:19 +00001298 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001299}
1300
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001301/* sets bit 0 in 0x6d */
1302static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1303{
1304 uint8_t old, new;
1305
1306 old = pci_read_byte(dev, 0x6d);
1307 new = old | 0x01;
1308 if (new == old)
1309 return 0;
1310
1311 rpci_write_byte(dev, 0x6d, new);
1312 if (pci_read_byte(dev, 0x6d) != new) {
1313 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1314 return 1;
1315 }
1316 return 0;
1317}
1318
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001319static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1320{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001321 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001322 if (enable_flash_nvidia_common(dev, name))
1323 return ERROR_NONFATAL;
1324 else
1325 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001326}
1327
Uwe Hermann372eeb52007-12-04 21:49:06 +00001328static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001329{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001330 uint32_t segctrl;
1331 uint8_t reg, old, new;
1332 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001333
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001334 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1335 reg = 0x8A;
1336 segctrl = pci_read_byte(dev, reg);
1337 if ((segctrl & 0x3) != 0x0) {
1338 if ((segctrl & 0xC) != 0x0) {
1339 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1340 err++;
1341 } else {
1342 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1343 rpci_write_byte(dev, reg, segctrl & 0xF0);
1344
1345 segctrl = pci_read_byte(dev, reg);
1346 if ((segctrl & 0x3) != 0x0) {
1347 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1348 reg, segctrl);
1349 err++;
1350 } else
1351 msg_pdbg("OK\n");
1352 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001353 }
1354
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001355 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1356 segctrl = pci_read_long(dev, reg);
1357 if ((segctrl & 0x33333333) == 0x00000000) {
1358 /* reads and writes are unlocked */
1359 continue;
1360 }
1361 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1362 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1363 err++;
1364 continue;
1365 }
1366 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1367 rpci_write_long(dev, reg, 0x00000000);
1368
1369 segctrl = pci_read_long(dev, reg);
1370 if ((segctrl & 0x33333333) != 0x00000000) {
1371 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1372 reg, segctrl);
1373 err++;
1374 } else
1375 msg_pdbg("OK\n");
1376 }
1377
1378 if (err > 0) {
1379 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
1380 programmer_may_write = 0;
1381 }
1382
1383 reg = 0x88;
1384 old = pci_read_byte(dev, reg);
1385 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001386 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001387 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001388 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1389 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001390 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001391 }
1392 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001393
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001394 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001395 err++;
1396
1397 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001398 return ERROR_NONFATAL;
1399 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001400 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001401}
1402
Joshua Roys85835d82010-09-15 14:47:56 +00001403static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1404{
1405 uint8_t tmp;
1406
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001407 internal_buses_supported = BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001408
1409 tmp = INB(0xc06);
1410 tmp |= 0x1;
1411 OUTB(tmp, 0xc06);
1412
1413 tmp = INB(0xc6f);
1414 tmp |= 0x40;
1415 OUTB(tmp, 0xc6f);
1416
1417 return 0;
1418}
1419
Uwe Hermann372eeb52007-12-04 21:49:06 +00001420/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1421static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001422{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001423 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001424 struct pci_dev *smbusdev;
1425
Uwe Hermann372eeb52007-12-04 21:49:06 +00001426 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001427 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001428
Uwe Hermanna7e05482007-05-09 10:17:44 +00001429 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001430 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001431 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001432 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001433
Uwe Hermann372eeb52007-12-04 21:49:06 +00001434 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001435 tmp = pci_read_byte(smbusdev, 0x79);
1436 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001437 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001438
Uwe Hermann372eeb52007-12-04 21:49:06 +00001439 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001440 tmp = pci_read_byte(dev, 0x48);
1441 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001442 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001443
Uwe Hermann372eeb52007-12-04 21:49:06 +00001444 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001445 tmp = INB(0xc6f);
1446 OUTB(tmp, 0xeb);
1447 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001448 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001449 OUTB(tmp, 0xc6f);
1450 OUTB(tmp, 0xeb);
1451 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001452
1453 return 0;
1454}
1455
Uwe Hermann372eeb52007-12-04 21:49:06 +00001456static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001457{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001458 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001459 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001460
Uwe Hermann372eeb52007-12-04 21:49:06 +00001461 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001462 val = pci_read_byte(dev, 0x88);
1463 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001464 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001465 val = pci_read_byte(dev, 0x8c);
1466 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001467 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001468 wordval = pci_read_word(dev, 0x90);
1469 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001470 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001471
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001472 if (enable_flash_nvidia_common(dev, name))
1473 return ERROR_NONFATAL;
1474 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001475 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001476}
1477
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001478/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001479 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1480 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1481 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001482 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001483static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001484{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001485 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001486 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001487
1488 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001489 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001490 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001491 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001492
Michael Karchercfa674f2010-02-25 11:38:23 +00001493 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001494 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001495 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001496 internal_buses_supported = BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001497 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001498 break;
1499 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001500 want_spi = 1;
1501 /* SPI is added in mcp6x_spi_init if it works.
1502 * Do we really want to disable LPC in this case?
1503 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001504 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001505 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001506 break;
1507 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001508 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001509 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001510 msg_pwarn("Flash bus type is unknown (none)\n");
1511 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to \n"
1512 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1513 "help us finish support for your chipset. Thanks.\n");
1514 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001515 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001516
1517 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001518#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001519 val |= (1 << 6);
1520 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001521 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001522#endif
1523
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001524 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001525 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001526
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001527 return ret;
1528}
1529
Uwe Hermann372eeb52007-12-04 21:49:06 +00001530static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001531{
Michael Karchercfa674f2010-02-25 11:38:23 +00001532 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001533
Uwe Hermanne823ee02007-06-05 15:02:18 +00001534 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001535 val = pci_read_byte(dev, 0x41);
1536 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001537 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001538
Michael Karchercfa674f2010-02-25 11:38:23 +00001539 val = pci_read_byte(dev, 0x43);
1540 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001541 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001542
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001543 return 0;
1544}
1545
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001546/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001547 * Usually on the x86 architectures (and on other PC-like platforms like some
1548 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1549 * Elan SC520 only a small piece of the system flash is mapped there, but the
1550 * complete flash is mapped somewhere below 1G. The position can be determined
1551 * by the BOOTCS PAR register.
1552 */
1553static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1554{
1555 int i, bootcs_found = 0;
1556 uint32_t parx = 0;
1557 void *mmcr;
1558
1559 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001560 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001561 if (mmcr == ERROR_PTR)
1562 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001563
1564 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1565 * BOOTCS region (PARx[31:29] = 100b)e
1566 */
1567 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001568 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001569 if ((parx >> 29) == 4) {
1570 bootcs_found = 1;
1571 break; /* BOOTCS found */
1572 }
1573 }
1574
1575 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1576 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1577 */
1578 if (bootcs_found) {
1579 if (parx & (1 << 25)) {
1580 parx &= (1 << 14) - 1; /* Mask [13:0] */
1581 flashbase = parx << 16;
1582 } else {
1583 parx &= (1 << 18) - 1; /* Mask [17:0] */
1584 flashbase = parx << 12;
1585 }
1586 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001587 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001588 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001589 }
1590
1591 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001592 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001593 return 0;
1594}
1595
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001596#endif
1597
Idwer Vollering326a0602011-06-18 18:45:41 +00001598/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001599const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001600#if defined(__i386__) || defined(__x86_64__)
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001601 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1602 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
1603 {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1604 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1605 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1606 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1607 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1608 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1609 {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1610 {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600},
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +01001611 {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001612 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1613 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1614 {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530},
1615 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1616 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1617 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1618 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1619 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1620 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1621 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
1622 {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540},
1623 {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540},
1624 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
1625 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1626 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
1627 {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540},
1628 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1629 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1630 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1631 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1632 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1633 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1634 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1635 {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540},
1636 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1637 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1638 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1639 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1640 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1641 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1642 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1643 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1644 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1645 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1646 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1647 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1648 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001649 /* Slave, should not be here, to fix known bug for A01. */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001650 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1651 {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1652 {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1653 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1654 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1655 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001656 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1657 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1658 * Until we have PCI device class matching or some fallback mechanism,
1659 * this is needed to get flashrom working on Tyan S2915 and maybe other
1660 * dual-MCP55 boards.
1661 */
1662#if 0
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001663 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001664#endif
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001665 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1666 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1667 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1668 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1669 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1670 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1671 {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1672 {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1673 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1674 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1675 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1676 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1677 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1678 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1679 {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1680 {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1681 {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1682 {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1683 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1684 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1685 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1686 {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001687 /* VIA northbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001688 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1689 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1690 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1691 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1692 {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge},
1693 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001694 /* VIA southbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001695 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586},
1696 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596},
1697 {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596},
1698 {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x},
1699 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
1700 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1701 {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x},
Stefan Tauner94d86652015-11-21 23:35:47 +00001702 {0x1106, 0x3287, OK, "VIA", "VT8251", enable_flash_vt823x},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001703 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1704 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1705 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1706 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1707 {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx},
1708 {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx},
1709 {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx},
1710 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1711 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1712 {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
1713 {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001714 {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001715 {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1716 {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1717 {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001718 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1719 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1720 {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6},
1721 {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6},
1722 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
1723 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
1724 {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6},
1725 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
1726 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
1727 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
1728 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6},
1729 {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6},
1730 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6},
1731 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6},
1732 {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6},
1733 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
1734 {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6},
1735 {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1736 {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1737 {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7},
1738 {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
1739 {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7},
1740 {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7},
1741 {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7},
1742 {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7},
1743 {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7},
1744 {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7},
1745 {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7},
1746 {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7},
1747 {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
1748 {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},
1749 {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7},
1750 {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7},
1751 {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7},
Stefan Tauner23e10b82016-01-23 16:16:49 +00001752 {0x8086, 0x1f38, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001753 {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1754 {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1755 {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
David Hendricksa1bccd82017-08-08 23:28:54 -07001756 {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001757 {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001758 {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7},
1759 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},
1760 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0},
1761 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345},
1762 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345},
1763 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345},
1764 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345},
1765 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345},
1766 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345},
1767 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345},
1768 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345},
1769 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345},
1770 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},