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Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermannb4dcb712009-05-13 11:36:06 +000015 */
16
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000017#if defined(__i386__) || defined(__x86_64__)
18
Uwe Hermannb4dcb712009-05-13 11:36:06 +000019#include <stdlib.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000020#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000021#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000022#include "hwaccess.h"
Uwe Hermannb4dcb712009-05-13 11:36:06 +000023
24#define BIOS_ROM_ADDR 0x04
25#define BIOS_ROM_DATA 0x08
26#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000027#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000028#define SELECT_REG_WINDOW 0x800
29
Uwe Hermannb4dcb712009-05-13 11:36:06 +000030#define PCI_VENDOR_ID_3COM 0x10b7
31
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000032static uint32_t io_base_addr = 0;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000033static uint32_t internal_conf;
34static uint16_t id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +000035
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000036const struct dev_entry nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000037 /* 3C90xB */
Michael Karcher84486392010-02-24 00:04:40 +000038 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
39 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
40 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
41 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
42 {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
43 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
44 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
45 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000046
47 /* 3C905C */
Michael Karcher84486392010-02-24 00:04:40 +000048 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000049
50 /* 3C980C */
Michael Karcher84486392010-02-24 00:04:40 +000051 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000052
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000053 {0},
Uwe Hermannb4dcb712009-05-13 11:36:06 +000054};
55
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000056static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
57 chipaddr addr);
58static uint8_t nic3com_chip_readb(const struct flashctx *flash,
59 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000060static const struct par_master par_master_nic3com = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000061 .chip_readb = nic3com_chip_readb,
62 .chip_readw = fallback_chip_readw,
63 .chip_readl = fallback_chip_readl,
64 .chip_readn = fallback_chip_readn,
65 .chip_writeb = nic3com_chip_writeb,
66 .chip_writew = fallback_chip_writew,
67 .chip_writel = fallback_chip_writel,
68 .chip_writen = fallback_chip_writen,
69};
70
David Hendricks8bb20212011-06-14 01:35:36 +000071static int nic3com_shutdown(void *data)
72{
73 /* 3COM 3C90xB cards need a special fixup. */
74 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
75 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
76 /* Select register window 3 and restore the receiver status. */
77 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
78 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
79 }
80
David Hendricks8bb20212011-06-14 01:35:36 +000081 return 0;
82}
83
Uwe Hermannb4dcb712009-05-13 11:36:06 +000084int nic3com_init(void)
85{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000086 struct pci_dev *dev = NULL;
87
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000088 if (rget_io_perms())
89 return 1;
Uwe Hermannb4dcb712009-05-13 11:36:06 +000090
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000091 dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
92 if (!dev)
93 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000094
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000095 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +000096 if (!io_base_addr)
97 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000098
99 id = dev->device_id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000100
101 /* 3COM 3C90xB cards need a special fixup. */
102 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +0000103 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000104 /* Select register window 3 and save the receiver status. */
105 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
106 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
107
108 /* Set receiver type to MII for full BIOS ROM access. */
109 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
110 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000111
112 /*
113 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
114 * cards form a 'register window' into one of multiple (usually 8)
115 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
116 */
117 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
118
David Hendricks8bb20212011-06-14 01:35:36 +0000119 if (register_shutdown(nic3com_shutdown, NULL))
120 return 1;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000121
122 max_rom_decode.parallel = 128 * 1024;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000123 register_par_master(&par_master_nic3com, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000124
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000125 return 0;
126}
127
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000128static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
129 chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000130{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000131 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000132 OUTB(val, io_base_addr + BIOS_ROM_DATA);
133}
134
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000135static uint8_t nic3com_chip_readb(const struct flashctx *flash,
136 const chipaddr addr)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000137{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000138 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
Uwe Hermannc7e8a0c2009-05-19 14:14:21 +0000139 return INB(io_base_addr + BIOS_ROM_DATA);
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000140}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000141
142#else
143#error PCI port I/O access is not supported on this architecture yet.
144#endif