blob: 91c8aa51e3de481b01836a2e237275e6e40abcae [file] [log] [blame]
Edward O'Callaghand97f87b2020-03-26 00:00:41 +11001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2020 The Chromium OS Authors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <stdlib.h>
18#include <stdint.h>
19#include <stdio.h>
20#include <string.h>
21#include <time.h>
22#include <errno.h>
23
24#include "programmer.h"
25#include "spi.h"
26#include "i2c_helper.h"
27
28
Shiyu Sun963a2912021-01-21 16:03:30 +110029#define MCU_I2C_SLAVE_ADDR 0x94
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110030#define REGISTER_ADDRESS (0x94 >> 1)
Angel Pons9785daa2021-05-09 18:44:55 +020031#define RTK_PAGE_SIZE 128
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110032#define MAX_SPI_WAIT_RETRIES 1000
33
Edward O'Callaghan413d6ec2020-05-04 13:01:54 +100034#define MCU_MODE 0x6F
Shiyu Sun10d71d92020-12-17 02:31:40 +110035#define MCU_ISP_MODE_MASK 0x80
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +100036#define START_WRITE_XFER 0xA0
37#define WRITE_XFER_STATUS_MASK 0x20
Edward O'Callaghan413d6ec2020-05-04 13:01:54 +100038
39#define MCU_DATA_PORT 0x70
40
41#define MAP_PAGE_BYTE2 0x64
42#define MAP_PAGE_BYTE1 0x65
43#define MAP_PAGE_BYTE0 0x66
44
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110045//opcodes
46#define OPCODE_READ 3
47#define OPCODE_WRITE 2
48
Shiyu Sun8a99a6e2020-10-07 00:42:59 +110049#define GPIO_CONFIG_ADDRESS 0x104F
50#define GPIO_VALUE_ADDRESS 0xFE3F
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110051
52struct realtek_mst_i2c_spi_data {
53 int fd;
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +100054 int reset;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110055};
56
57static int realtek_mst_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len)
58{
59 i2c_buffer_t data;
60 if (i2c_buffer_t_fill(&data, buf, len))
61 return SPI_GENERIC_ERROR;
62
63 return i2c_write(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR;
64}
65
66static int realtek_mst_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len)
67{
68 i2c_buffer_t data;
69 if (i2c_buffer_t_fill(&data, buf, len))
70 return SPI_GENERIC_ERROR;
71
72 return i2c_read(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR;
73}
74
75static int get_fd_from_context(const struct flashctx *flash)
76{
77 if (!flash || !flash->mst || !flash->mst->spi.data) {
78 msg_perr("Unable to extract fd from flash context.\n");
79 return SPI_GENERIC_ERROR;
80 }
Shiyu Sun963a2912021-01-21 16:03:30 +110081 const struct realtek_mst_i2c_spi_data *data =
Edward O'Callaghand97f87b2020-03-26 00:00:41 +110082 (const struct realtek_mst_i2c_spi_data *)flash->mst->spi.data;
83
84 return data->fd;
85}
86
87static int realtek_mst_i2c_spi_write_register(int fd, uint8_t reg, uint8_t value)
88{
89 uint8_t command[] = { reg, value };
90 return realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2);
91}
92
93static int realtek_mst_i2c_spi_read_register(int fd, uint8_t reg, uint8_t *value)
94{
95 uint8_t command[] = { reg };
96 int ret = realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1);
97 ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1);
98
99 return ret ? SPI_GENERIC_ERROR : 0;
100}
101
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000102static int realtek_mst_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask,
103 int target, int multiplier)
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100104{
105 uint8_t val;
106 int tried = 0;
107 int ret = 0;
108 do {
109 ret |= realtek_mst_i2c_spi_read_register(fd, offset, &val);
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000110 } while (!ret && ((val & mask) != target) && ++tried < (MAX_SPI_WAIT_RETRIES*multiplier));
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100111
112 if (tried == MAX_SPI_WAIT_RETRIES) {
113 msg_perr("%s: Time out on sending command.\n", __func__);
114 return -MAX_SPI_WAIT_RETRIES;
115 }
116
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000117 return (val & mask) != target ? SPI_GENERIC_ERROR : ret;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100118}
119
120static int realtek_mst_i2c_spi_enter_isp_mode(int fd)
121{
Shiyu Sun10d71d92020-12-17 02:31:40 +1100122 int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, MCU_ISP_MODE_MASK);
123 /* wait for ISP mode enter success */
124 ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, MCU_ISP_MODE_MASK, MCU_ISP_MODE_MASK, 1);
125
126 if (ret)
127 return ret;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100128
129 // set internal osc divider register to default to speed up MCU
130 // 0x06A0 = 0x74
131 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F);
132 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x06);
133 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0xA0);
134 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, 0x74);
135
136 return ret;
137}
138
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000139static int realtek_mst_i2c_execute_write(int fd)
140{
141 int ret = realtek_mst_i2c_spi_write_register(fd, MCU_MODE, START_WRITE_XFER);
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000142 ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, WRITE_XFER_STATUS_MASK, 0, 1);
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000143 return ret;
144}
145
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100146static int realtek_mst_i2c_spi_reset_mpu(int fd)
147{
Shiyu Sun10d71d92020-12-17 02:31:40 +1100148 uint8_t mcu_mode_val;
149 int ret = realtek_mst_i2c_spi_read_register(fd, MCU_MODE, &mcu_mode_val);
150 if (ret || (mcu_mode_val & MCU_ISP_MODE_MASK) == 0) {
151 msg_perr("%s: MST not in ISP mode, cannot perform MCU reset.\n", __func__);
152 return SPI_GENERIC_ERROR;
153 }
154
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100155 // 0xFFEE[1] = 1;
156 uint8_t val = 0;
157 ret |= realtek_mst_i2c_spi_read_register(fd, 0xEE, &val);
158 ret |= realtek_mst_i2c_spi_write_register(fd, 0xEE, (val & 0xFD) | 0x02);
159 return ret;
160}
161
Shiyu Sun8a99a6e2020-10-07 00:42:59 +1100162static int realtek_mst_i2c_spi_select_indexed_register(int fd, uint16_t address)
163{
164 int ret = 0;
165
166 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, 0x9F);
167 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, address >> 8);
168 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF4, address & 0xFF);
169
170 return ret;
171}
172
173static int realtek_mst_i2c_spi_write_indexed_register(int fd, uint16_t address, uint8_t val)
174{
175 int ret = 0;
176
177 ret |= realtek_mst_i2c_spi_select_indexed_register(fd, address);
178 ret |= realtek_mst_i2c_spi_write_register(fd, 0xF5, val);
179
180 return ret;
181}
182
183static int realtek_mst_i2c_spi_read_indexed_register(int fd, uint16_t address, uint8_t *val)
184{
185 int ret = 0;
186
187 ret |= realtek_mst_i2c_spi_select_indexed_register(fd, address);
188 ret |= realtek_mst_i2c_spi_read_register(fd, 0xF5, val);
189
190 return ret;
191}
192
193
194/* Toggle the GPIO pin 88, this could be routed to different controls like write
195 * protection or a led. */
196static int realtek_mst_i2c_spi_toggle_gpio_88_strap(int fd, bool toggle)
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100197{
198 int ret = 0;
199 uint8_t val = 0;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100200
Shiyu Sun8a99a6e2020-10-07 00:42:59 +1100201 /* Read register 0x104F into val. */
202 ret |= realtek_mst_i2c_spi_read_indexed_register(fd, GPIO_CONFIG_ADDRESS, &val);
203 /* Write 0x104F[3:0] = b0001 to enable the toggle of pin value. */
204 ret |= realtek_mst_i2c_spi_write_indexed_register(fd, GPIO_CONFIG_ADDRESS, (val & 0xF0) | 0x01);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100205
Shiyu Sun8a99a6e2020-10-07 00:42:59 +1100206 /* Read register 0xFE3F into val. */
207 ret |= realtek_mst_i2c_spi_read_indexed_register(fd, GPIO_VALUE_ADDRESS, &val);
208 /* Write 0xFE3F[0] = b|toggle| to toggle pin value to low/high. */
209 ret |= realtek_mst_i2c_spi_write_indexed_register(fd, GPIO_VALUE_ADDRESS, (val & 0xFE) | toggle);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100210
211 return ret;
212}
213
214static int realtek_mst_i2c_spi_send_command(const struct flashctx *flash,
215 unsigned int writecnt, unsigned int readcnt,
216 const unsigned char *writearr,
217 unsigned char *readarr)
218{
219 unsigned i;
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000220 int max_timeout_mul = 1;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100221 int ret = 0;
222
223 if (writecnt > 4 || readcnt > 3 || writecnt == 0) {
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100224 return SPI_GENERIC_ERROR;
225 }
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100226
227 int fd = get_fd_from_context(flash);
228 if (fd < 0)
229 return SPI_GENERIC_ERROR;
230
Edward O'Callaghan76c582d2020-05-06 15:24:25 +1000231 /* First byte of writearr should be the spi opcode value, followed by the value to write. */
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100232 writecnt--;
Edward O'Callaghan76c582d2020-05-06 15:24:25 +1000233
234 /**
235 * Before dispatching a SPI opcode the MCU register 0x60 requires
236 * the following configuration byte set:
237 *
238 * BIT0 - start [0] , end [1].
239 * BITS[1-4] - counts.
240 * BITS[5-7] - opcode type.
241 *
242 * | bit7 | bit6 | bit5 |
243 * +------+------+------+
244 * | 0 | 1 | 0 | ~ JEDEC_RDID,REMS,READ
245 * | 0 | 1 | 1 | ~ JEDEC_WRSR
246 * | 1 | 0 | 1 | ~ JEDEC_.. erasures.
247 */
248 uint8_t ctrl_reg_val = (writecnt << 3) | (readcnt << 1);
249 switch (writearr[0]) {
250 /* WREN isn't a supported somehow? ignore it. */
251 case JEDEC_WREN: return 0;
252 /* WRSR requires BIT6 && BIT5 set. */
253 case JEDEC_WRSR:
254 ctrl_reg_val |= (1 << 5);
255 ctrl_reg_val |= (2 << 5);
256 break;
257 /* Erasures require BIT7 && BIT5 set. */
Edward O'Callaghan76c582d2020-05-06 15:24:25 +1000258 case JEDEC_CE_C7:
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000259 max_timeout_mul *= 20; /* chip erasures take much longer! */
260 /* FALLTHRU */
261 case JEDEC_CE_60:
Edward O'Callaghan76c582d2020-05-06 15:24:25 +1000262 case JEDEC_BE_52:
263 case JEDEC_BE_D8:
264 case JEDEC_BE_D7:
265 case JEDEC_SE:
266 ctrl_reg_val |= (1 << 5);
267 ctrl_reg_val |= (4 << 5);
268 break;
269 default:
270 /* Otherwise things like RDID,REMS,READ require BIT6 */
271 ctrl_reg_val |= (2 << 5);
272 }
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100273 ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val);
Edward O'Callaghan76c582d2020-05-06 15:24:25 +1000274 ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, writearr[0]); /* opcode */
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100275
276 for (i = 0; i < writecnt; ++i)
277 ret |= realtek_mst_i2c_spi_write_register(fd, 0x64 + i, writearr[i + 1]);
278 ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, ctrl_reg_val | 0x1);
279 if (ret)
280 return ret;
281
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000282 ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01, 0, max_timeout_mul);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100283 if (ret)
284 return ret;
285
286 for (i = 0; i < readcnt; ++i)
287 ret |= realtek_mst_i2c_spi_read_register(fd, 0x67 + i, &readarr[i]);
288
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100289 return ret;
290}
291
Edward O'Callaghane3afd772020-12-29 19:00:24 +1100292static int realtek_mst_i2c_spi_map_page(int fd, uint32_t addr)
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100293{
294 int ret = 0;
Edward O'Callaghane3afd772020-12-29 19:00:24 +1100295
296 uint8_t block_idx = (addr >> 16) & 0xff;
297 uint8_t page_idx = (addr >> 8) & 0xff;
298 uint8_t byte_idx = addr & 0xff;
299
Edward O'Callaghan413d6ec2020-05-04 13:01:54 +1000300 ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE2, block_idx);
301 ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE1, page_idx);
302 ret |= realtek_mst_i2c_spi_write_register(fd, MAP_PAGE_BYTE0, byte_idx);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100303
304 return ret ? SPI_GENERIC_ERROR : 0;
305}
306
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000307static int realtek_mst_i2c_spi_write_page(int fd, uint8_t reg, const uint8_t *buf, unsigned int len)
308{
309 /**
310 * Using static buffer with maximum possible size,
311 * extra byte is needed for prefixing the data port register at index 0.
312 */
Angel Pons9785daa2021-05-09 18:44:55 +0200313 uint8_t wbuf[RTK_PAGE_SIZE + 1] = { MCU_DATA_PORT };
314 if (len > RTK_PAGE_SIZE)
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000315 return SPI_GENERIC_ERROR;
316
317 memcpy(&wbuf[1], buf, len);
318
319 return realtek_mst_i2c_spi_write_data(fd, REGISTER_ADDRESS, wbuf, len + 1);
320}
321
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100322static int realtek_mst_i2c_spi_read(struct flashctx *flash, uint8_t *buf,
323 unsigned int start, unsigned int len)
324{
325 unsigned i;
326 int ret = 0;
327
328 if (start & 0xff)
329 return default_spi_read(flash, buf, start, len);
330
331 int fd = get_fd_from_context(flash);
332 if (fd < 0)
333 return SPI_GENERIC_ERROR;
334
335 start--;
336 ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x46); // **
337 ret |= realtek_mst_i2c_spi_write_register(fd, 0x61, OPCODE_READ);
Edward O'Callaghane3afd772020-12-29 19:00:24 +1100338 ret |= realtek_mst_i2c_spi_map_page(fd, start);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100339 ret |= realtek_mst_i2c_spi_write_register(fd, 0x6a, 0x03);
340 ret |= realtek_mst_i2c_spi_write_register(fd, 0x60, 0x47); // **
341 if (ret)
342 return ret;
343
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000344 ret = realtek_mst_i2c_spi_wait_command_done(fd, 0x60, 0x01, 0, 1);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100345 if (ret)
346 return ret;
347
348 /**
349 * The first byte is just a null, probably a status code?
350 * Advance the read by a offset of one byte and continue.
351 */
352 uint8_t dummy;
Edward O'Callaghan413d6ec2020-05-04 13:01:54 +1000353 realtek_mst_i2c_spi_read_register(fd, MCU_DATA_PORT, &dummy);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100354
Angel Pons9785daa2021-05-09 18:44:55 +0200355 for (i = 0; i < len; i += RTK_PAGE_SIZE) {
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100356 ret |= realtek_mst_i2c_spi_read_data(fd, REGISTER_ADDRESS,
Angel Pons9785daa2021-05-09 18:44:55 +0200357 buf + i, min(len - i, RTK_PAGE_SIZE));
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100358 if (ret)
359 return ret;
360 }
361
362 return ret;
363}
364
365static int realtek_mst_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf,
366 unsigned int start, unsigned int len)
367{
368 unsigned i;
369 int ret = 0;
370
371 if (start & 0xff)
372 return default_spi_write_256(flash, buf, start, len);
373
374 int fd = get_fd_from_context(flash);
375 if (fd < 0)
376 return SPI_GENERIC_ERROR;
377
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000378 ret |= realtek_mst_i2c_spi_write_register(fd, 0x6D, 0x02); /* write opcode */
Angel Pons9785daa2021-05-09 18:44:55 +0200379 ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, (RTK_PAGE_SIZE - 1)); /* fit len=256 */
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100380
Angel Pons9785daa2021-05-09 18:44:55 +0200381 for (i = 0; i < len; i += RTK_PAGE_SIZE) {
382 uint16_t page_len = min(len - i, RTK_PAGE_SIZE);
383 if (len - i < RTK_PAGE_SIZE)
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000384 ret |= realtek_mst_i2c_spi_write_register(fd, 0x71, page_len-1);
Edward O'Callaghane3afd772020-12-29 19:00:24 +1100385 ret |= realtek_mst_i2c_spi_map_page(fd, start + i);
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000386 if (ret)
387 break;
388
389 /* Wait for empty buffer. */
Edward O'Callaghana9abaae2020-05-07 11:42:56 +1000390 ret |= realtek_mst_i2c_spi_wait_command_done(fd, MCU_MODE, 0x10, 0x10, 1);
Edward O'Callaghan6a5472c2020-05-06 16:16:47 +1000391 if (ret)
392 break;
393
394 ret |= realtek_mst_i2c_spi_write_page(fd, MCU_DATA_PORT,
395 buf + i, page_len);
396 if (ret)
397 break;
398 ret |= realtek_mst_i2c_execute_write(fd);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100399 if (ret)
400 break;
401 }
402
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100403 return ret;
404}
405
406static int realtek_mst_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf,
407 unsigned int start, unsigned int len)
408{
409 msg_perr("%s: AAI write function is not supported.\n", __func__);
410 return SPI_GENERIC_ERROR;
411}
412
Anastasia Klimchuk45e0a072021-05-25 13:53:25 +1000413static const struct spi_master spi_master_i2c_realtek_mst = {
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100414 .max_data_read = 16,
415 .max_data_write = 8,
416 .command = realtek_mst_i2c_spi_send_command,
417 .multicommand = default_spi_send_multicommand,
418 .read = realtek_mst_i2c_spi_read,
419 .write_256 = realtek_mst_i2c_spi_write_256,
420 .write_aai = realtek_mst_i2c_spi_write_aai,
421};
422
423static int realtek_mst_i2c_spi_shutdown(void *data)
424{
425 int ret = 0;
Shiyu Sun963a2912021-01-21 16:03:30 +1100426 struct realtek_mst_i2c_spi_data *realtek_mst_data =
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100427 (struct realtek_mst_i2c_spi_data *)data;
428 int fd = realtek_mst_data->fd;
Shiyu Sun6cad6082021-01-21 16:08:11 +1100429 ret |= realtek_mst_i2c_spi_toggle_gpio_88_strap(fd, false);
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000430 if (realtek_mst_data->reset) {
Shiyu Sun59052702021-01-21 16:31:32 +1100431 /*
432 * Return value for reset mpu is not checked since
433 * the return value is not guaranteed to be 0 on a
434 * success reset. Currently there is no way to fix
435 * that. For more details see b:147402710.
436 */
437 realtek_mst_i2c_spi_reset_mpu(fd);
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000438 }
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100439 i2c_close(fd);
440 free(data);
441
442 return ret;
443}
444
Angel Ponsb81dbc52021-05-02 19:03:58 +0200445static int get_params(int *reset, int *enter_isp)
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100446{
Angel Ponsb81dbc52021-05-02 19:03:58 +0200447 char *reset_str = NULL, *isp_str = NULL;
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100448 int ret = SPI_GENERIC_ERROR;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100449
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000450 reset_str = extract_programmer_param("reset-mcu");
451 if (reset_str) {
Angel Pons922e28b2021-05-02 19:05:30 +0200452 if (reset_str[0] == '1') {
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000453 *reset = 1;
Angel Pons922e28b2021-05-02 19:05:30 +0200454 } else if (reset_str[0] == '0') {
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000455 *reset = 0;
Angel Pons922e28b2021-05-02 19:05:30 +0200456 } else {
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000457 msg_perr("%s: Incorrect param format, reset-mcu=1 or 0.\n", __func__);
458 ret = SPI_GENERIC_ERROR;
459 }
Angel Pons922e28b2021-05-02 19:05:30 +0200460 } else {
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000461 *reset = 0; /* Default behaviour is no MCU reset on tear-down. */
Angel Pons922e28b2021-05-02 19:05:30 +0200462 }
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000463 free(reset_str);
464
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100465 isp_str = extract_programmer_param("enter-isp");
466 if (isp_str) {
Angel Pons922e28b2021-05-02 19:05:30 +0200467 if (isp_str[0] == '1') {
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100468 *enter_isp = 1;
Angel Pons922e28b2021-05-02 19:05:30 +0200469 } else if (isp_str[0] == '0') {
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100470 *enter_isp = 0;
Angel Pons922e28b2021-05-02 19:05:30 +0200471 } else {
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100472 msg_perr("%s: Incorrect param format, enter-isp=1 or 0.\n", __func__);
473 ret = SPI_GENERIC_ERROR;
474 }
Angel Pons922e28b2021-05-02 19:05:30 +0200475 } else {
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100476 *enter_isp = 1; /* Default behaviour is enter ISP on setup. */
Angel Pons922e28b2021-05-02 19:05:30 +0200477 }
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100478 free(isp_str);
479
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100480 return ret;
481}
482
483int realtek_mst_i2c_spi_init(void)
484{
485 int ret = 0;
Angel Ponsb81dbc52021-05-02 19:03:58 +0200486 int reset = 0, enter_isp = 0;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100487
Angel Ponsb81dbc52021-05-02 19:03:58 +0200488 if (get_params(&reset, &enter_isp))
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100489 return SPI_GENERIC_ERROR;
490
Angel Ponsb81dbc52021-05-02 19:03:58 +0200491 int fd = i2c_open_from_programmer_params(REGISTER_ADDRESS, 0);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100492 if (fd < 0)
493 return fd;
494
Shiyu Sun3e4f8d72020-10-21 04:10:58 +1100495 if (enter_isp) {
496 ret |= realtek_mst_i2c_spi_enter_isp_mode(fd);
497 if (ret)
498 return ret;
499 }
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100500
Shiyu Sun6cad6082021-01-21 16:08:11 +1100501 ret |= realtek_mst_i2c_spi_toggle_gpio_88_strap(fd, true);
502 if (ret) {
503 msg_perr("Unable to toggle gpio 88 strap to True.\n");
504 return ret;
505 }
506
Angel Pons3bd47522021-06-07 12:33:53 +0200507 struct realtek_mst_i2c_spi_data *data = calloc(1, sizeof(*data));
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100508 if (!data) {
509 msg_perr("Unable to allocate space for extra SPI master data.\n");
510 return SPI_GENERIC_ERROR;
511 }
512
513 data->fd = fd;
Edward O'Callaghan3ba19b32020-09-24 15:50:21 +1000514 data->reset = reset;
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100515 ret |= register_shutdown(realtek_mst_i2c_spi_shutdown, data);
Anastasia Klimchuk45e0a072021-05-25 13:53:25 +1000516 ret |= register_spi_master(&spi_master_i2c_realtek_mst, data);
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100517
518 return ret;
519}