blob: b5f205083cacdfc7835be47eac1926cd32dad1e7 [file] [log] [blame]
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S
5 * Copyright (C) 2011, 2014 Stefan Tauner
6 *
7 * Based on nicinctel_spi.c and ichspi.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000017 */
18
19/*
20 * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet
21 * 3.3.1.4: General EEPROM Software Access
22 * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface)
23 * 7.4: Register Descriptions
24 */
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010025/*
26 * Datasheet: Intel Ethernet Controller I210: Datasheet
27 * 8.4.3: EEPROM-Mode Read Register
28 * 8.4.6: EEPROM-Mode Write Register
29 * Write process inspired on kernel e1000_i210.c
30 */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000031
32#include <stdlib.h>
33#include <unistd.h>
34#include "flash.h"
35#include "spi.h"
36#include "programmer.h"
37#include "hwaccess.h"
38
39#define PCI_VENDOR_ID_INTEL 0x8086
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010040#define MEMMAP_SIZE 0x1c /* Only EEC, EERD and EEWR are needed. */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000041
42#define EEC 0x10 /* EEPROM/Flash Control Register */
43#define EERD 0x14 /* EEPROM Read Register */
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010044#define EEWR 0x18 /* EEPROM Write Register */
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000045
46/* EPROM/Flash Control Register bits */
47#define EE_SCK 0
48#define EE_CS 1
49#define EE_SI 2
50#define EE_SO 3
51#define EE_REQ 6
52#define EE_GNT 7
53#define EE_PRES 8
54#define EE_SIZE 11
55#define EE_SIZE_MASK 0xf
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010056#define EE_FLUPD 23
57#define EE_FLUDONE 26
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000058
59/* EEPROM Read Register bits */
60#define EERD_START 0
61#define EERD_DONE 1
62#define EERD_ADDR 2
63#define EERD_DATA 16
64
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010065/* EEPROM Write Register bits */
66#define EEWR_CMDV 0
67#define EEWR_DONE 1
68#define EEWR_ADDR 2
69#define EEWR_DATA 16
70
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000071#define BIT(x) (1<<x)
Stefan Tauner8d21ff12015-01-10 09:33:06 +000072#define EE_PAGE_MASK 0x3f
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000073
74static uint8_t *nicintel_eebar;
75static struct pci_dev *nicintel_pci;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010076static bool done_i20_write = false;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000077
78#define UNPROG_DEVICE 0x1509
79
Nico Huber4343e7d2017-10-10 17:38:07 +020080/*
81 * Warning: is_i210() below makes assumptions on these PCI ids.
82 * It may have to be updated when this list is extended.
83 */
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020084static const struct dev_entry nics_intel_ee[] = {
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000085 {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"},
86 {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"},
87 {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"},
88 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"},
89 {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"},
90 {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"},
Angel Ponsc1173782021-05-02 15:09:20 +020091 {PCI_VENDOR_ID_INTEL, 0x1531, OK, "Intel", "I210 Gigabit Network Connection Unprogrammed"},
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +010092 {PCI_VENDOR_ID_INTEL, 0x1532, NT, "Intel", "I211 Gigabit Network Connection Unprogrammed"},
93 {PCI_VENDOR_ID_INTEL, 0x1533, OK, "Intel", "I210 Gigabit Network Connection"},
94 {PCI_VENDOR_ID_INTEL, 0x1536, NT, "Intel", "I210 Gigabit Network Connection SERDES Fiber"},
95 {PCI_VENDOR_ID_INTEL, 0x1537, NT, "Intel", "I210 Gigabit Network Connection SERDES Backplane"},
96 {PCI_VENDOR_ID_INTEL, 0x1538, NT, "Intel", "I210 Gigabit Network Connection SGMII"},
97 {PCI_VENDOR_ID_INTEL, 0x1539, NT, "Intel", "I211 Gigabit Network Connection"},
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +000098 {0},
99};
100
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100101static inline bool is_i210(uint16_t device_id)
102{
Nico Huber4343e7d2017-10-10 17:38:07 +0200103 return (device_id & 0xfff0) == 0x1530;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100104}
105
106static int nicintel_ee_probe_i210(struct flashctx *flash)
107{
108 /* Emulated eeprom has a fixed size of 4 KB */
109 flash->chip->total_size = 4;
110 flash->chip->page_size = flash->chip->total_size * 1024;
111 flash->chip->tested = TEST_OK_PREW;
112 flash->chip->gran = write_gran_1byte_implicit_erase;
113 flash->chip->block_erasers->eraseblocks[0].size = flash->chip->page_size;
114 flash->chip->block_erasers->eraseblocks[0].count = 1;
115
116 return 1;
117}
118
119static int nicintel_ee_probe_82580(struct flashctx *flash)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000120{
121 if (nicintel_pci->device_id == UNPROG_DEVICE)
122 flash->chip->total_size = 16; /* Fall back to minimum supported size. */
123 else {
124 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
125 tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK);
126 switch (tmp) {
127 case 7:
128 flash->chip->total_size = 16;
129 break;
130 case 8:
131 flash->chip->total_size = 32;
132 break;
133 default:
134 msg_cerr("Unsupported chip size 0x%x\n", tmp);
135 return 0;
136 }
137 }
138
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000139 flash->chip->page_size = EE_PAGE_MASK + 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000140 flash->chip->tested = TEST_OK_PREW;
141 flash->chip->gran = write_gran_1byte_implicit_erase;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000142 flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1);
143 flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1);
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000144
145 return 1;
146}
147
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100148#define MAX_ATTEMPTS 10000000
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000149static int nicintel_ee_read_word(unsigned int addr, uint16_t *data)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000150{
151 uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR);
152 pci_mmio_writel(tmp, nicintel_eebar + EERD);
153
154 /* Poll done flag. 10.000.000 cycles seem to be enough. */
155 uint32_t i;
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100156 for (i = 0; i < MAX_ATTEMPTS; i++) {
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000157 tmp = pci_mmio_readl(nicintel_eebar + EERD);
158 if (tmp & BIT(EERD_DONE)) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000159 *data = (tmp >> EERD_DATA) & 0xffff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000160 return 0;
161 }
162 }
163
164 return -1;
165}
166
167static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len)
168{
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000169 uint16_t data;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000170
171 /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address
172 * explicitly at the start (and also at the end in the loop below). */
173 if (addr & 1) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000174 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000175 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000176 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000177 addr++;
178 len--;
179 }
180
181 while (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000182 if (nicintel_ee_read_word(addr / 2, &data))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000183 return -1;
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000184 *buf++ = data & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000185 addr++;
186 len--;
187 if (len > 0) {
Stefan Tauner3e6b7bb2015-01-25 23:45:14 +0000188 *buf++ = (data >> 8) & 0xff;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000189 addr++;
190 len--;
191 }
192 }
193
194 return 0;
195}
196
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100197static int nicintel_ee_write_word_i210(unsigned int addr, uint16_t data)
198{
199 uint32_t eewr;
200
201 eewr = addr << EEWR_ADDR;
202 eewr |= data << EEWR_DATA;
203 eewr |= BIT(EEWR_CMDV);
204 pci_mmio_writel(eewr, nicintel_eebar + EEWR);
205
206 programmer_delay(5);
David Hendricks79d838d2017-09-27 09:25:34 -0700207 int i;
208 for (i = 0; i < MAX_ATTEMPTS; i++)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100209 if (pci_mmio_readl(nicintel_eebar + EEWR) & BIT(EEWR_DONE))
210 return 0;
211 return -1;
212}
213
Nico Huber4343e7d2017-10-10 17:38:07 +0200214static int nicintel_ee_write_i210(struct flashctx *flash, const uint8_t *buf,
215 unsigned int addr, unsigned int len)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100216{
217 done_i20_write = true;
218
219 if (addr & 1) {
220 uint16_t data;
221
222 if (nicintel_ee_read_word(addr / 2, &data)) {
223 msg_perr("Timeout reading heading byte\n");
224 return -1;
225 }
226
227 data &= 0xff;
228 data |= (buf ? (buf[0]) : 0xff) << 8;
229
230 if (nicintel_ee_write_word_i210(addr / 2, data)) {
231 msg_perr("Timeout writing heading word\n");
232 return -1;
233 }
234
235 if (buf)
236 buf ++;
237 addr ++;
238 len --;
239 }
240
241 while (len > 0) {
242 uint16_t data;
243
244 if (len == 1) {
245 if (nicintel_ee_read_word(addr / 2, &data)) {
246 msg_perr("Timeout reading tail byte\n");
247 return -1;
248 }
249
250 data &= 0xff00;
251 data |= buf ? (buf[0]) : 0xff;
252 } else {
253 if (buf)
254 data = buf[0] | (buf[1] << 8);
255 else
256 data = 0xffff;
257 }
258
259 if (nicintel_ee_write_word_i210(addr / 2, data)) {
260 msg_perr("Timeout writing Shadow RAM\n");
261 return -1;
262 }
263
264 if (buf)
265 buf += 2;
266 if (len > 2)
267 len -= 2;
268 else
269 len = 0;
270 addr += 2;
271 }
272
273 return 0;
274}
275
Nico Huber89622672017-10-10 18:05:55 +0200276static int nicintel_ee_erase_i210(struct flashctx *flash, unsigned int addr, unsigned int len)
277{
278 return nicintel_ee_write_i210(flash, NULL, addr, len);
279}
280
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000281static int nicintel_ee_bitset(int reg, int bit, bool val)
282{
283 uint32_t tmp;
284
285 tmp = pci_mmio_readl(nicintel_eebar + reg);
286 if (val)
287 tmp |= BIT(bit);
288 else
289 tmp &= ~BIT(bit);
290 pci_mmio_writel(tmp, nicintel_eebar + reg);
291
292 return -1;
293}
294
295/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */
296static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso)
297{
298 uint8_t out = 0x0;
299
300 int i;
301 for (i = 7; i >= 0; i--) {
302 nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i));
303 nicintel_ee_bitset(EEC, EE_SCK, 1);
304 if (miso != NULL) {
305 uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC);
306 if (tmp & BIT(EE_SO))
307 out |= BIT(i);
308 }
309 nicintel_ee_bitset(EEC, EE_SCK, 0);
310 }
311
312 if (miso != NULL)
313 *miso = out;
314
315 return 0;
316}
317
318/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */
319static int nicintel_ee_ready(void)
320{
321 unsigned int i;
322 for (i = 0; i < 1000; i++) {
323 nicintel_ee_bitset(EEC, EE_CS, 0);
324
325 nicintel_ee_bitbang(JEDEC_RDSR, NULL);
326 uint8_t rdsr;
327 nicintel_ee_bitbang(0x00, &rdsr);
328
329 nicintel_ee_bitset(EEC, EE_CS, 1);
330 programmer_delay(1);
331 if (!(rdsr & SPI_SR_WIP)) {
332 return 0;
333 }
334 }
335 return -1;
336}
337
338/* Requests direct access to the SPI pins. */
339static int nicintel_ee_req(void)
340{
341 uint32_t tmp;
342 nicintel_ee_bitset(EEC, EE_REQ, 1);
343
344 tmp = pci_mmio_readl(nicintel_eebar + EEC);
345 if (!(tmp & BIT(EE_GNT))) {
346 msg_perr("Enabling eeprom access failed.\n");
347 return 1;
348 }
349
350 nicintel_ee_bitset(EEC, EE_SCK, 0);
351 return 0;
352}
353
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100354static int nicintel_ee_write_82580(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000355{
356 if (nicintel_ee_req())
357 return -1;
358
359 int ret = -1;
360 if (nicintel_ee_ready())
361 goto out;
362
363 while (len > 0) {
364 /* WREN */
365 nicintel_ee_bitset(EEC, EE_CS, 0);
366 nicintel_ee_bitbang(JEDEC_WREN, NULL);
367 nicintel_ee_bitset(EEC, EE_CS, 1);
368 programmer_delay(1);
369
370 /* data */
371 nicintel_ee_bitset(EEC, EE_CS, 0);
372 nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL);
373 nicintel_ee_bitbang((addr >> 8) & 0xff, NULL);
374 nicintel_ee_bitbang(addr & 0xff, NULL);
375 while (len > 0) {
376 nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL);
377 len--;
378 addr++;
Stefan Tauner8d21ff12015-01-10 09:33:06 +0000379 if (!(addr & EE_PAGE_MASK))
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000380 break;
381 }
382 nicintel_ee_bitset(EEC, EE_CS, 1);
383 programmer_delay(1);
384 if (nicintel_ee_ready())
385 goto out;
386 }
387 ret = 0;
388out:
389 nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */
390 return ret;
391}
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100392
Nico Huber89622672017-10-10 18:05:55 +0200393static int nicintel_ee_erase_82580(struct flashctx *flash, unsigned int addr, unsigned int len)
394{
395 return nicintel_ee_write_82580(flash, NULL, addr, len);
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100396}
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000397
Nico Huber89622672017-10-10 18:05:55 +0200398static const struct opaque_master opaque_master_nicintel_ee_82580 = {
399 .probe = nicintel_ee_probe_82580,
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000400 .read = nicintel_ee_read,
Nico Huber89622672017-10-10 18:05:55 +0200401 .write = nicintel_ee_write_82580,
402 .erase = nicintel_ee_erase_82580,
403};
404
405static const struct opaque_master opaque_master_nicintel_ee_i210 = {
406 .probe = nicintel_ee_probe_i210,
407 .read = nicintel_ee_read,
408 .write = nicintel_ee_write_i210,
409 .erase = nicintel_ee_erase_i210,
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000410};
411
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100412static int nicintel_ee_shutdown_i210(void *arg)
413{
414 if (!done_i20_write)
415 return 0;
416
417 uint32_t flup = pci_mmio_readl(nicintel_eebar + EEC);
418
419 flup |= BIT(EE_FLUPD);
420 pci_mmio_writel(flup, nicintel_eebar + EEC);
421
David Hendricks79d838d2017-09-27 09:25:34 -0700422 int i;
423 for (i = 0; i < MAX_ATTEMPTS; i++)
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100424 if (pci_mmio_readl(nicintel_eebar + EEC) & BIT(EE_FLUDONE))
425 return 0;
426
427 msg_perr("Flash update failed\n");
428
429 return -1;
430}
431
Nico Huber89622672017-10-10 18:05:55 +0200432static int nicintel_ee_shutdown_82580(void *eecp)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000433{
434 uint32_t old_eec = *(uint32_t *)eecp;
435 /* Request bitbanging and unselect the chip first to be safe. */
436 if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1))
437 return -1;
438
439 /* Try to restore individual bits we care about. */
440 int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK));
441 ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI));
442 ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS));
443 /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */
444 ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ));
445
446 free(eecp);
447 return ret;
448}
449
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200450static int nicintel_ee_init(void)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000451{
452 if (rget_io_perms())
453 return 1;
454
455 struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0);
456 if (!dev)
457 return 1;
458
459 uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
460 if (!io_base_addr)
461 return 1;
462
Nico Huber89622672017-10-10 18:05:55 +0200463 if (!is_i210(dev->device_id)) {
464 nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE);
465 if (!nicintel_eebar)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000466 return 1;
Nico Huber89622672017-10-10 18:05:55 +0200467
468 nicintel_pci = dev;
469 if ((dev->device_id != UNPROG_DEVICE)) {
470 uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC);
471
472 /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting
473 the EE_PRES definition),
474 and 3.3.1.7 for possible recovery. */
475 if (!(eec & BIT(EE_PRES))) {
476 msg_perr("Controller reports no EEPROM is present.\n");
477 return 1;
478 }
479
480 uint32_t *eecp = malloc(sizeof(uint32_t));
481 if (eecp == NULL)
482 return 1;
483 *eecp = eec;
484
485 if (register_shutdown(nicintel_ee_shutdown_82580, eecp))
486 return 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000487 }
488
Anastasia Klimchuk9309bed2021-05-13 12:28:47 +1000489 return register_opaque_master(&opaque_master_nicintel_ee_82580, NULL);
Nico Huber89622672017-10-10 18:05:55 +0200490 } else {
491 nicintel_eebar = rphysmap("Intel i210 NIC w/ emulated EEPROM",
492 io_base_addr + 0x12000, MEMMAP_SIZE);
493 if (!nicintel_eebar)
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000494 return 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000495
Ricardo Ribalda Delgado9fe1fb72017-03-23 15:11:22 +0100496 if (register_shutdown(nicintel_ee_shutdown_i210, NULL))
497 return 1;
498
Anastasia Klimchuk9309bed2021-05-13 12:28:47 +1000499 return register_opaque_master(&opaque_master_nicintel_ee_i210, NULL);
Nico Huber89622672017-10-10 18:05:55 +0200500 }
501
502 return 1;
Ricardo Ribalda Delgado2a41f0a2014-07-28 20:35:21 +0000503}
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200504
505const struct programmer_entry programmer_nicintel_eeprom = {
506 .name = "nicintel_eeprom",
507 .type = PCI,
508 .devs.dev = nics_intel_ee,
509 .init = nicintel_ee_init,
510 .map_flash_region = fallback_map,
511 .unmap_flash_region = fallback_unmap,
512 .delay = internal_delay,
513};