blob: b590f1db95554035eac1ee105540449a8fb65106 [file] [log] [blame]
Shiyu Sun13a2ef62020-03-19 14:37:57 +11001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2020 The Chromium OS Authors
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <stdlib.h>
18#include <stdint.h>
19#include <stdio.h>
20#include <string.h>
21#include <time.h>
22#include <errno.h>
23
24#include "programmer.h"
25#include "spi.h"
26#include "i2c_helper.h"
27
28#define REGISTER_ADDRESS (0x94 >> 1)
29#define PAGE_ADDRESS (0x9e >> 1)
Angel Ponscbe8a392021-04-17 15:32:12 +020030#define LSPCON_PAGE_SIZE 256
Shiyu Sun13a2ef62020-03-19 14:37:57 +110031#define MAX_SPI_WAIT_RETRIES 1000
32
33#define CLT2_SPI 0x82
34#define SPIEDID_BASE_ADDR2 0x8d
35#define ROMADDR_BYTE1 0x8e
36#define ROMADDR_BYTE2 0x8f
37#define SWSPI_WDATA 0x90
38 #define SWSPI_WDATA_CLEAR_STATUS 0x00
39 #define SWSPI_WDATA_WRITE_REGISTER 0x01
40 #define SWSPI_WDATA_READ_REGISTER 0x05
41 #define SWSPI_WDATA_ENABLE_REGISTER 0x06
42 #define SWSPI_WDATA_SECTOR_ERASE 0x20
43 #define SWSPI_WDATA_PROTECT_BP 0x8c
44#define SWSPI_RDATA 0x91
45#define SWSPI_LEN 0x92
46#define SWSPICTL 0x93
47 #define SWSPICTL_ACCESS_TRIGGER 1
48 #define SWSPICTL_CLEAR_PTR (1 << 1)
49 #define SWSPICTL_NO_READ (1 << 2)
50 #define SWSPICTL_ENABLE_READBACK (1 << 3)
51 #define SWSPICTL_MOT (1 << 4)
52#define SPISTATUS 0x9e
53 #define SPISTATUS_BYTE_PROGRAM_FINISHED 0
54 #define SPISTATUS_BYTE_PROGRAM_IN_IF 1
55 #define SPISTATUS_BYTE_PROGRAM_SEND_DONE (1 << 1)
56 #define SPISTATUS_SECTOR_ERASE_FINISHED 0
57 #define SPISTATUS_SECTOR_ERASE_IN_IF (1 << 2)
58 #define SPISTATUS_SECTOR_ERASE_SEND_DONE (1 << 3)
59 #define SPISTATUS_CHIP_ERASE_FINISHED 0
60 #define SPISTATUS_CHIP_ERASE_IN_IF (1 << 4)
61 #define SPISTATUS_CHIP_ERASE_SEND_DONE (1 << 5)
62 #define SPISTATUS_FW_UPDATE_ENABLE (1 << 6)
63#define WRITE_PROTECTION 0xb3
64 #define WRITE_PROTECTION_ON 0
65 #define WRITE_PROTECTION_OFF 0x10
66#define MPU 0xbc
67#define PAGE_HW_WRITE 0xda
68 #define PAGE_HW_WRITE_DISABLE 0
69 #define PAGE_HW_COFIG_REGISTER 0xaa
70 #define PAGE_HW_WRITE_ENABLE 0x55
71
72struct lspcon_i2c_spi_data {
73 int fd;
74};
75
76typedef struct {
77 uint8_t command;
78 const uint8_t *data;
79 uint8_t data_size;
80 uint8_t control;
81} packet_t;
82
83static int lspcon_i2c_spi_write_data(int fd, uint16_t addr, void *buf, uint16_t len)
84{
85 i2c_buffer_t data;
86 if (i2c_buffer_t_fill(&data, buf, len))
87 return SPI_GENERIC_ERROR;
88
89 return i2c_write(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR;
90}
91
92static int lspcon_i2c_spi_read_data(int fd, uint16_t addr, void *buf, uint16_t len)
93{
94 i2c_buffer_t data;
95 if (i2c_buffer_t_fill(&data, buf, len))
96 return SPI_GENERIC_ERROR;
97
98 return i2c_read(fd, addr, &data) == len ? 0 : SPI_GENERIC_ERROR;
99}
100
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000101static int get_fd_from_context(const struct flashctx *flash)
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100102{
103 if (!flash || !flash->mst || !flash->mst->spi.data) {
104 msg_perr("Unable to extract fd from flash context.\n");
105 return SPI_GENERIC_ERROR;
106 }
107 const struct lspcon_i2c_spi_data *data =
108 (const struct lspcon_i2c_spi_data *)flash->mst->spi.data;
109
110 return data->fd;
111}
112
113static int lspcon_i2c_spi_write_register(int fd, uint8_t i2c_register, uint8_t value)
114{
115 uint8_t command[] = { i2c_register, value };
116 return lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 2);
117}
118
119static int lspcon_i2c_spi_read_register(int fd, uint8_t i2c_register, uint8_t *value)
120{
121 uint8_t command[] = { i2c_register };
122 int ret = lspcon_i2c_spi_write_data(fd, REGISTER_ADDRESS, command, 1);
123 ret |= lspcon_i2c_spi_read_data(fd, REGISTER_ADDRESS, value, 1);
124
125 return ret ? SPI_GENERIC_ERROR : 0;
126}
127
128static int lspcon_i2c_spi_register_control(int fd, packet_t *packet)
129{
130 int i;
131 int ret = lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->command);
132 if (ret)
133 return ret;
134
135 /* Higher 4 bits are read size. */
136 int write_size = packet->data_size & 0x0f;
137 for (i = 0; i < write_size; ++i) {
138 ret |= lspcon_i2c_spi_write_register(fd, SWSPI_WDATA, packet->data[i]);
139 }
140
141 ret |= lspcon_i2c_spi_write_register(fd, SWSPI_LEN, packet->data_size);
142 ret |= lspcon_i2c_spi_write_register(fd, SWSPICTL, packet->control);
143
144 return ret;
145}
146
147static int lspcon_i2c_spi_wait_command_done(int fd, unsigned int offset, int mask)
148{
149 uint8_t val;
150 int tried = 0;
151 int ret = 0;
152 do {
153 ret |= lspcon_i2c_spi_read_register(fd, offset, &val);
Edward O'Callaghan94991d82020-04-24 13:39:55 +1000154 } while (!ret && (val & mask) && ++tried < MAX_SPI_WAIT_RETRIES);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100155
156 if (tried == MAX_SPI_WAIT_RETRIES) {
Shiyu Sun7f87f9f2020-04-30 16:51:09 +1000157 msg_perr("%s: Time out on sending command.\n", __func__);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100158 return -MAX_SPI_WAIT_RETRIES;
159 }
160
161 return (val & mask) ? SPI_GENERIC_ERROR : ret;
162}
163
164static int lspcon_i2c_spi_wait_rom_free(int fd)
165{
166 uint8_t val;
167 int tried = 0;
168 int ret = 0;
169 ret |= lspcon_i2c_spi_wait_command_done(fd, SPISTATUS,
170 SPISTATUS_SECTOR_ERASE_IN_IF | SPISTATUS_SECTOR_ERASE_SEND_DONE);
171 if (ret)
172 return ret;
173
174 do {
175 packet_t packet = { SWSPI_WDATA_READ_REGISTER, NULL, 0, SWSPICTL_ACCESS_TRIGGER };
176 ret |= lspcon_i2c_spi_register_control(fd, &packet);
177 ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER);
178 ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &val);
179 } while (!ret && (val & SWSPICTL_ACCESS_TRIGGER) && ++tried < MAX_SPI_WAIT_RETRIES);
180
181 if (tried == MAX_SPI_WAIT_RETRIES) {
Shiyu Sun7f87f9f2020-04-30 16:51:09 +1000182 msg_perr("%s: Time out on waiting ROM free.\n", __func__);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100183 return -MAX_SPI_WAIT_RETRIES;
184 }
185
186 return (val & SWSPICTL_ACCESS_TRIGGER) ? SPI_GENERIC_ERROR : ret;
187}
188
189static int lspcon_i2c_spi_toggle_register_protection(int fd, int toggle)
190{
191 return lspcon_i2c_spi_write_register(fd, WRITE_PROTECTION,
192 toggle ? WRITE_PROTECTION_OFF : WRITE_PROTECTION_ON);
193}
194
195static int lspcon_i2c_spi_enable_write_status_register(int fd)
196{
197 int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1);
198 packet_t packet = {
199 SWSPI_WDATA_ENABLE_REGISTER, NULL, 0, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ };
200 ret |= lspcon_i2c_spi_register_control(fd, &packet);
201 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0);
202
203 return ret;
204}
205
206static int lspcon_i2c_spi_enable_write_status_register_protection(int fd)
207{
208 int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1);
209 uint8_t data[] = { SWSPI_WDATA_PROTECT_BP };
210 packet_t packet = {
211 SWSPI_WDATA_WRITE_REGISTER, data, 1, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ };
212 ret |= lspcon_i2c_spi_register_control(fd, &packet);
213 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0);
214
215 return ret;
216}
217
218static int lspcon_i2c_spi_disable_protection(int fd)
219{
220 int ret = lspcon_i2c_spi_toggle_register_protection(fd, 1);
221 uint8_t data[] = { SWSPI_WDATA_CLEAR_STATUS };
222 packet_t packet = {
223 SWSPI_WDATA_WRITE_REGISTER, data, 1, SWSPICTL_ACCESS_TRIGGER | SWSPICTL_NO_READ };
224 ret |= lspcon_i2c_spi_register_control(fd, &packet);
225 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0);
226
227 return ret;
228}
229
230static int lspcon_i2c_spi_disable_hw_write(int fd)
231{
232 return lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_DISABLE);
233}
234
235static int lspcon_i2c_spi_enable_write_protection(int fd)
236{
237 int ret = lspcon_i2c_spi_enable_write_status_register(fd);
238 ret |= lspcon_i2c_spi_enable_write_status_register_protection(fd);
239 ret |= lspcon_i2c_spi_wait_rom_free(fd);
240 ret |= lspcon_i2c_spi_disable_hw_write(fd);
241
242 return ret;
243}
244
245static int lspcon_i2c_spi_disable_all_protection(int fd)
246{
247 int ret = lspcon_i2c_spi_enable_write_status_register(fd);
248 ret |= lspcon_i2c_spi_disable_protection(fd);
249 ret |= lspcon_i2c_spi_wait_rom_free(fd);
250
251 return ret;
252}
253
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000254static int lspcon_i2c_spi_send_command(const struct flashctx *flash,
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100255 unsigned int writecnt, unsigned int readcnt,
256 const unsigned char *writearr,
257 unsigned char *readarr)
258{
259 unsigned int i;
260 if (writecnt > 16 || readcnt > 16 || writecnt == 0) {
Shiyu Sun7f87f9f2020-04-30 16:51:09 +1000261 msg_perr("%s: Invalid read/write count for send command.\n",
262 __func__);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100263 return SPI_GENERIC_ERROR;
264 }
265
266 int fd = get_fd_from_context(flash);
267 if (fd < 0)
268 return SPI_GENERIC_ERROR;
269
270 int ret = lspcon_i2c_spi_disable_all_protection(fd);
271 ret |= lspcon_i2c_spi_enable_write_status_register(fd);
272 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 1);
273
274 /* First byte of writearr shuld be the command value, followed by the value to write.
275 Read length occupies 4 bit and represents 16 level, thus if read 1 byte,
276 read length should be set 0. */
277 packet_t packet = {
278 writearr[0], &writearr[1], (writecnt - 1) | ((readcnt - 1) << 4),
279 SWSPICTL_ACCESS_TRIGGER | (readcnt ? 0 : SWSPICTL_NO_READ),
280 };
281
282 ret |= lspcon_i2c_spi_register_control(fd, &packet);
283 ret |= lspcon_i2c_spi_wait_command_done(fd, SWSPICTL, SWSPICTL_ACCESS_TRIGGER);
284 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0);
285 if (ret)
286 return ret;
287
288 for (i = 0; i < readcnt; ++i) {
289 ret |= lspcon_i2c_spi_read_register(fd, SWSPI_RDATA, &readarr[i]);
290 }
291
292 ret |= lspcon_i2c_spi_wait_rom_free(fd);
293
294 return ret;
295}
296
297static int lspcon_i2c_spi_enable_hw_write(int fd)
298{
299 int ret = 0;
300 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_COFIG_REGISTER);
301 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, PAGE_HW_WRITE_ENABLE);
302 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x50);
303 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x41);
304 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x52);
305 ret |= lspcon_i2c_spi_write_register(fd, PAGE_HW_WRITE, 0x44);
306
307 return ret;
308}
309
310static int lspcon_i2c_clt2_spi_reset(int fd)
311{
312 int ret = 0;
313 ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x20);
314 struct timespec wait_100ms = { 0, (unsigned)1e8 };
315 nanosleep(&wait_100ms, NULL);
316 ret |= lspcon_i2c_spi_write_register(fd, CLT2_SPI, 0x00);
317
318 return ret;
319}
320
Peter Marheinedb2a6392021-06-11 09:27:30 +1000321static int lspcon_i2c_spi_set_mpu_active(int fd, int running)
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100322{
323 int ret = 0;
Peter Marheinedb2a6392021-06-11 09:27:30 +1000324 // Cmd mode
325 ret |= lspcon_i2c_spi_write_register(fd, MPU, 0xc0);
326 // Stop or release MPU
327 ret |= lspcon_i2c_spi_write_register(fd, MPU, running ? 0 : 0x40);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100328
329 return ret;
330}
331
332static int lspcon_i2c_spi_map_page(int fd, unsigned int offset)
333{
334 int ret = 0;
Angel Ponscbe8a392021-04-17 15:32:12 +0200335 /* Page number byte, need to / LSPCON_PAGE_SIZE. */
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100336 ret |= lspcon_i2c_spi_write_register(fd, ROMADDR_BYTE1, (offset >> 8) & 0xff);
337 ret |= lspcon_i2c_spi_write_register(fd, ROMADDR_BYTE2, (offset >> 16));
338
339 return ret ? SPI_GENERIC_ERROR : 0;
340}
341
342static int lspcon_i2c_spi_read(struct flashctx *flash, uint8_t *buf,
343 unsigned int start, unsigned int len)
344{
345 unsigned int i;
346 int ret = 0;
347 if (start & 0xff)
348 return default_spi_read(flash, buf, start, len);
349
350 int fd = get_fd_from_context(flash);
351 if (fd < 0)
352 return SPI_GENERIC_ERROR;
353
Angel Ponscbe8a392021-04-17 15:32:12 +0200354 for (i = 0; i < len; i += LSPCON_PAGE_SIZE) {
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100355 ret |= lspcon_i2c_spi_map_page(fd, start + i);
Angel Ponscbe8a392021-04-17 15:32:12 +0200356 ret |= lspcon_i2c_spi_read_data(fd, PAGE_ADDRESS, buf + i, min(len - i, LSPCON_PAGE_SIZE));
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100357 }
358
359 return ret;
360}
361
362static int lspcon_i2c_spi_write_page(int fd, const uint8_t *buf, unsigned int len)
363{
364 /**
365 * Using static buffer with maximum possible size,
366 * extra byte is needed for prefixing zero at index 0.
367 */
Angel Ponscbe8a392021-04-17 15:32:12 +0200368 uint8_t write_buffer[LSPCON_PAGE_SIZE + 1] = { 0 };
369 if (len > LSPCON_PAGE_SIZE)
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100370 return SPI_GENERIC_ERROR;
371
372 /* First byte represents the writing offset and should always be zero. */
373 memcpy(&write_buffer[1], buf, len);
374
375 return lspcon_i2c_spi_write_data(fd, PAGE_ADDRESS, write_buffer, len + 1);
376}
377
378static int lspcon_i2c_spi_write_256(struct flashctx *flash, const uint8_t *buf,
379 unsigned int start, unsigned int len)
380{
381 int ret = 0;
382 if (start & 0xff)
383 return default_spi_write_256(flash, buf, start, len);
384
385 int fd = get_fd_from_context(flash);
386 if (fd < 0)
387 return SPI_GENERIC_ERROR;
388
389 ret |= lspcon_i2c_spi_disable_all_protection(fd);
390 /* Enable hardware write and reset clt2SPI interface. */
391 ret |= lspcon_i2c_spi_enable_hw_write(fd);
392 ret |= lspcon_i2c_clt2_spi_reset(fd);
393
Angel Ponscbe8a392021-04-17 15:32:12 +0200394 for (unsigned int i = 0; i < len; i += LSPCON_PAGE_SIZE) {
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100395 ret |= lspcon_i2c_spi_map_page(fd, start + i);
Angel Ponscbe8a392021-04-17 15:32:12 +0200396 ret |= lspcon_i2c_spi_write_page(fd, buf + i, min(len - i, LSPCON_PAGE_SIZE));
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100397 }
398
399 ret |= lspcon_i2c_spi_enable_write_protection(fd);
400 ret |= lspcon_i2c_spi_disable_hw_write(fd);
401
402 return ret;
403}
404
405static int lspcon_i2c_spi_write_aai(struct flashctx *flash, const uint8_t *buf,
406 unsigned int start, unsigned int len)
407{
Shiyu Sun7f87f9f2020-04-30 16:51:09 +1000408 msg_perr("%s: AAI write function is not supported.\n",
409 __func__);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100410 return SPI_GENERIC_ERROR;
411}
412
Nico Huber90739d12021-05-11 17:53:34 +0200413static const struct spi_master spi_master_i2c_lspcon = {
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100414 .max_data_read = 16,
415 .max_data_write = 12,
416 .command = lspcon_i2c_spi_send_command,
417 .multicommand = default_spi_send_multicommand,
418 .read = lspcon_i2c_spi_read,
419 .write_256 = lspcon_i2c_spi_write_256,
420 .write_aai = lspcon_i2c_spi_write_aai,
421};
422
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100423static int lspcon_i2c_spi_shutdown(void *data)
424{
425 int ret = 0;
426 struct lspcon_i2c_spi_data *lspcon_data =
427 (struct lspcon_i2c_spi_data *)data;
428 int fd = lspcon_data->fd;
Peter Marheinedb2a6392021-06-11 09:27:30 +1000429
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100430 ret |= lspcon_i2c_spi_enable_write_protection(fd);
431 ret |= lspcon_i2c_spi_toggle_register_protection(fd, 0);
Peter Marheinedb2a6392021-06-11 09:27:30 +1000432 ret |= lspcon_i2c_spi_set_mpu_active(fd, 1);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100433 i2c_close(fd);
434 free(data);
435
436 return ret;
437}
438
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200439static int lspcon_i2c_spi_init(void)
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100440{
Angel Ponsdb232952021-05-02 18:56:45 +0200441 int fd = i2c_open_from_programmer_params(REGISTER_ADDRESS, 0);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100442 if (fd < 0)
443 return fd;
444
Peter Marheinedb2a6392021-06-11 09:27:30 +1000445 int ret = lspcon_i2c_spi_set_mpu_active(fd, 0);
Edward O'Callaghana25c13c2020-04-17 14:10:55 +1000446 if (ret) {
Peter Marheinedb2a6392021-06-11 09:27:30 +1000447 msg_perr("%s: call to set_mpu_active failed.\n", __func__);
Angel Ponsc7dd1702021-05-02 19:00:37 +0200448 i2c_close(fd);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100449 return ret;
Edward O'Callaghana25c13c2020-04-17 14:10:55 +1000450 }
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100451
Angel Pons3bd47522021-06-07 12:33:53 +0200452 struct lspcon_i2c_spi_data *data = calloc(1, sizeof(*data));
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100453 if (!data) {
454 msg_perr("Unable to allocate space for extra SPI master data.\n");
Angel Ponsc7dd1702021-05-02 19:00:37 +0200455 i2c_close(fd);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100456 return SPI_GENERIC_ERROR;
457 }
458
459 data->fd = fd;
Edward O'Callaghana25c13c2020-04-17 14:10:55 +1000460
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100461 ret |= register_shutdown(lspcon_i2c_spi_shutdown, data);
Nico Huber90739d12021-05-11 17:53:34 +0200462 ret |= register_spi_master(&spi_master_i2c_lspcon, data);
Shiyu Sun13a2ef62020-03-19 14:37:57 +1100463
464 return ret;
465}
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200466
467const struct programmer_entry programmer_lspcon_i2c_spi = {
468 .name = "lspcon_i2c_spi",
469 .type = OTHER,
470 .devs.note = "Device files /dev/i2c-*.\n",
471 .init = lspcon_i2c_spi_init,
472 .map_flash_region = fallback_map,
473 .unmap_flash_region = fallback_unmap,
474 .delay = internal_delay,
475};