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Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00001/*
2 * This file is part of the flashrom project.
3 *
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +00004 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00005 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00006 * Copyright (C) 2008 coresystems GmbH
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +00007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000016 */
17
18/*
19 * Contains the ITE IT87* SPI specific routines
20 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000024#include <string.h>
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +000025#include <stdlib.h>
Vadim Girlin4dd0f902013-08-24 12:18:17 +000026#include <errno.h>
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000027#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000028#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000030#include "hwaccess.h"
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000031#include "spi.h"
32
33#define ITE_SUPERIO_PORT1 0x2e
34#define ITE_SUPERIO_PORT2 0x4e
35
Edward O'Callaghan779045d2020-11-17 18:11:47 +110036#define CHIP_ID_BYTE1_REG 0x20
37#define CHIP_ID_BYTE2_REG 0x21
38#define CHIP_VER_REG 0x22
39
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +110040struct it8716f_spi_data {
Edward O'Callaghanb2b45072020-11-17 18:38:15 +110041 uint16_t flashport;
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +110042 /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
43 int fast_spi;
44};
45
46static int get_data_from_context(const struct flashctx *flash, struct it8716f_spi_data **data)
47{
48 if (!flash || !flash->mst || !flash->mst->spi.data) {
49 msg_perr("Unable to extract fd from flash context.\n");
50 return SPI_GENERIC_ERROR;
51 }
52 *data = (struct it8716f_spi_data *)flash->mst->spi.data;
53
54 return 0;
55}
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000056
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000057/* Helper functions for most recent ITE IT87xx Super I/O chips */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000058void enter_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000059{
Andriy Gapon65c1b862008-05-22 13:22:45 +000060 OUTB(0x87, port);
61 OUTB(0x01, port);
62 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000063 if (port == ITE_SUPERIO_PORT1)
Andriy Gapon65c1b862008-05-22 13:22:45 +000064 OUTB(0x55, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000065 else
Andriy Gapon65c1b862008-05-22 13:22:45 +000066 OUTB(0xaa, port);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000067}
68
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000069void exit_conf_mode_ite(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000070{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000071 sio_write(port, 0x02, 0x02);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +000072}
73
Jacob Garberbeeb8bc2019-06-21 15:24:17 -060074static uint16_t probe_id_ite(uint16_t port)
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000075{
76 uint16_t id;
77
78 enter_conf_mode_ite(port);
79 id = sio_read(port, CHIP_ID_BYTE1_REG) << 8;
80 id |= sio_read(port, CHIP_ID_BYTE2_REG);
81 exit_conf_mode_ite(port);
82
83 return id;
84}
85
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000086void probe_superio_ite(void)
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000087{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000088 struct superio s = {0};
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000089 uint16_t ite_ports[] = {ITE_SUPERIO_PORT1, ITE_SUPERIO_PORT2, 0};
90 uint16_t *i = ite_ports;
91
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000092 s.vendor = SUPERIO_VENDOR_ITE;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000093 for (; *i; i++) {
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +000094 s.port = *i;
95 s.model = probe_id_ite(s.port);
96 switch (s.model >> 8) {
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000097 case 0x82:
98 case 0x86:
99 case 0x87:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000100 /* FIXME: Print revision for all models? */
Stefan Tauner352e50b2013-02-22 15:58:45 +0000101 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port 0x%x\n", s.model, s.port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000102 register_superio(s);
103 break;
104 case 0x85:
Stefan Tauner352e50b2013-02-22 15:58:45 +0000105 msg_pdbg("Found ITE EC, ID 0x%04hx, Rev 0x%02x on port 0x%x.\n",
106 s.model, sio_read(s.port, CHIP_VER_REG), s.port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000107 register_superio(s);
108 break;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000109 }
110 }
111
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000112 return;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000113}
114
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100115/* Page size is usually 256 bytes */
116static int it8716f_spi_page_program(struct flashctx *flash, const uint8_t *buf, unsigned int start)
117{
118 unsigned int i;
119 int result;
120 chipaddr bios = flash->virtual_memory;
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100121 struct it8716f_spi_data *data;
122
123 if (get_data_from_context(flash, &data) < 0)
124 return SPI_GENERIC_ERROR;
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100125
126 result = spi_write_enable(flash);
127 if (result)
128 return result;
129 /* FIXME: The command below seems to be redundant or wrong. */
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100130 OUTB(0x06, data->flashport + 1);
131 OUTB(((2 + (data->fast_spi ? 1 : 0)) << 4), data->flashport);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100132 for (i = 0; i < flash->chip->page_size; i++)
133 mmio_writeb(buf[i], (void *)(bios + start + i));
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100134 OUTB(0, data->flashport);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100135 /* Wait until the Write-In-Progress bit is cleared.
136 * This usually takes 1-10 ms, so wait in 1 ms steps.
137 */
138 while (spi_read_status_register(flash) & SPI_SR_WIP)
139 programmer_delay(1000);
140 return 0;
141}
142
143/*
144 * The IT8716F only supports commands with length 1,2,4,5 bytes including
145 * command byte and can not read more than 3 bytes from the device.
146 *
147 * This function expects writearr[0] to be the first byte sent to the device,
148 * whereas the IT8716F splits commands internally into address and non-address
149 * commands with the address in inverse wire order. That's why the register
150 * ordering in case 4 and 5 may seem strange.
151 */
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000152static int it8716f_spi_send_command(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000153 unsigned int writecnt, unsigned int readcnt,
154 const unsigned char *writearr,
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100155 unsigned char *readarr)
156{
157 uint8_t busy, writeenc;
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100158 struct it8716f_spi_data *data;
159
160 if (get_data_from_context(flash, &data) < 0)
161 return SPI_GENERIC_ERROR;
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100162
163 do {
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100164 busy = INB(data->flashport) & 0x80;
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100165 } while (busy);
166 if (readcnt > 3) {
167 msg_pinfo("%s called with unsupported readcnt %i.\n",
168 __func__, readcnt);
169 return SPI_INVALID_LENGTH;
170 }
171 switch (writecnt) {
172 case 1:
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100173 OUTB(writearr[0], data->flashport + 1);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100174 writeenc = 0x0;
175 break;
176 case 2:
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100177 OUTB(writearr[0], data->flashport + 1);
178 OUTB(writearr[1], data->flashport + 7);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100179 writeenc = 0x1;
180 break;
181 case 4:
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100182 OUTB(writearr[0], data->flashport + 1);
183 OUTB(writearr[1], data->flashport + 4);
184 OUTB(writearr[2], data->flashport + 3);
185 OUTB(writearr[3], data->flashport + 2);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100186 writeenc = 0x2;
187 break;
188 case 5:
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100189 OUTB(writearr[0], data->flashport + 1);
190 OUTB(writearr[1], data->flashport + 4);
191 OUTB(writearr[2], data->flashport + 3);
192 OUTB(writearr[3], data->flashport + 2);
193 OUTB(writearr[4], data->flashport + 7);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100194 writeenc = 0x3;
195 break;
196 default:
197 msg_pinfo("%s called with unsupported writecnt %i.\n",
198 __func__, writecnt);
199 return SPI_INVALID_LENGTH;
200 }
201 /*
202 * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
203 * Note:
204 * We can't use writecnt directly, but have to use a strange encoding.
205 */
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100206 OUTB(((0x4 + (data->fast_spi ? 1 : 0)) << 4)
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100207 | ((readcnt & 0x3) << 2) | (writeenc), data->flashport);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100208
209 if (readcnt > 0) {
210 unsigned int i;
211
212 do {
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100213 busy = INB(data->flashport) & 0x80;
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100214 } while (busy);
215
216 for (i = 0; i < readcnt; i++)
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100217 readarr[i] = INB(data->flashport + 5 + i);
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100218 }
219
220 return 0;
221}
222
223/*
224 * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles
225 * Need to read this big flash using firmware cycles 3 byte at a time.
226 */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000227static int it8716f_spi_chip_read(struct flashctx *flash, uint8_t *buf,
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100228 unsigned int start, unsigned int len)
229{
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100230 struct it8716f_spi_data *data;
231
232 if (get_data_from_context(flash, &data) < 0)
233 return SPI_GENERIC_ERROR;
234
235 data->fast_spi = 0;
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100236
237 /* FIXME: Check if someone explicitly requested to use IT87 SPI although
238 * the mainboard does not use IT87 SPI translation. This should be done
239 * via a programmer parameter for the internal programmer.
240 */
241 if ((flash->chip->total_size * 1024 > 512 * 1024)) {
242 default_spi_read(flash, buf, start, len);
243 } else {
244 mmio_readn((void *)(flash->virtual_memory + start), buf, len);
245 }
246
247 return 0;
248}
249
Mark Marshallf20b7be2014-05-09 21:16:21 +0000250static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf,
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100251 unsigned int start, unsigned int len)
252{
253 const struct flashchip *chip = flash->chip;
254 /*
255 * IT8716F only allows maximum of 512 kb SPI chip size for memory
256 * mapped access. It also can't write more than 1+3+256 bytes at once,
257 * so page_size > 256 bytes needs a fallback.
258 * FIXME: Split too big page writes into chunks IT87* can handle instead
259 * of degrading to single-byte program.
260 * FIXME: Check if someone explicitly requested to use IT87 SPI although
261 * the mainboard does not use IT87 SPI translation. This should be done
262 * via a programmer parameter for the internal programmer.
263 */
264 if ((chip->total_size * 1024 > 512 * 1024) || (chip->page_size > 256)) {
265 spi_chip_write_1(flash, buf, start, len);
266 } else {
267 unsigned int lenhere;
268
269 if (start % chip->page_size) {
270 /* start to the end of the page or to start + len,
271 * whichever is smaller.
272 */
273 lenhere = min(len, chip->page_size - start % chip->page_size);
274 spi_chip_write_1(flash, buf, start, lenhere);
275 start += lenhere;
276 len -= lenhere;
277 buf += lenhere;
278 }
279
280 while (len >= chip->page_size) {
281 it8716f_spi_page_program(flash, buf, start);
282 start += chip->page_size;
283 len -= chip->page_size;
284 buf += chip->page_size;
285 }
286 if (len)
287 spi_chip_write_1(flash, buf, start, len);
288 }
289
290 return 0;
291}
Michael Karcherb9dbe482011-05-11 17:07:07 +0000292
Nico Huber90739d12021-05-11 17:53:34 +0200293static const struct spi_master spi_master_it87xx = {
Edward O'Callaghand4d36572020-10-09 13:00:17 +1100294 .max_data_read = 3,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000295 .max_data_write = MAX_DATA_UNSPECIFIED,
296 .command = it8716f_spi_send_command,
297 .multicommand = default_spi_send_multicommand,
298 .read = it8716f_spi_chip_read,
299 .write_256 = it8716f_spi_chip_write_256,
Nico Huber504215b2017-04-22 00:13:15 +0200300 .write_aai = spi_chip_write_1,
Michael Karcherb9dbe482011-05-11 17:07:07 +0000301};
302
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100303
304static int it8716f_shutdown(void *data)
305{
306 free(data);
307 return 0;
308}
309
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000310static uint16_t it87spi_probe(uint16_t port)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000311{
312 uint8_t tmp = 0;
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000313 uint16_t flashport = 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000314
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000315 enter_conf_mode_ite(port);
Elyes HAOUAS0cacb112019-02-04 12:16:38 +0100316
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000317 char *param = extract_programmer_param("dualbiosindex");
318 if (param != NULL) {
319 sio_write(port, 0x07, 0x07); /* Select GPIO LDN */
320 tmp = sio_read(port, 0xEF);
321 if (*param == '\0') { /* Print current setting only. */
322 free(param);
323 } else {
324 char *dualbiosindex_suffix;
325 errno = 0;
326 long chip_index = strtol(param, &dualbiosindex_suffix, 0);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000327 if (errno != 0 || *dualbiosindex_suffix != '\0' || chip_index < 0 || chip_index > 1) {
328 msg_perr("DualBIOS: Invalid chip index requested - choose 0 or 1.\n");
Angel Pons51261542020-10-19 14:20:36 +0200329 free(param);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000330 exit_conf_mode_ite(port);
331 return 1;
332 }
Angel Pons51261542020-10-19 14:20:36 +0200333 free(param);
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000334 if (chip_index != (tmp & 1)) {
335 msg_pdbg("DualBIOS: Previous chip index: %d\n", tmp & 1);
336 sio_write(port, 0xEF, (tmp & 0xFE) | chip_index);
337 tmp = sio_read(port, 0xEF);
338 if ((tmp & 1) != chip_index) {
339 msg_perr("DualBIOS: Chip selection failed.\n");
340 exit_conf_mode_ite(port);
341 return 1;
342 }
343 }
344 }
345 msg_pinfo("DualBIOS: Selected chip: %d\n", tmp & 1);
346 }
347
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000348 /* NOLDN, reg 0x24, mask out lowest bit (suspend) */
349 tmp = sio_read(port, 0x24) & 0xFE;
Carl-Daniel Hailfinger2e681602011-09-08 00:00:29 +0000350 /* Check if LPC->SPI translation is active. */
351 if (!(tmp & 0x0e)) {
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000352 msg_pdbg("No IT87* serial flash segment enabled.\n");
353 exit_conf_mode_ite(port);
354 /* Nothing to do. */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000355 return 0;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000356 }
357 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
358 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
359 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
360 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
361 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
362 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
363 msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n",
364 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
365 msg_pdbg("LPC write to serial flash %sabled\n",
366 (tmp & 1 << 4) ? "en" : "dis");
367 /* The LPC->SPI force write enable below only makes sense for
368 * non-programmer mode.
369 */
370 /* If any serial flash segment is enabled, enable writing. */
371 if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
372 msg_pdbg("Enabling LPC write to serial flash\n");
373 tmp |= 1 << 4;
374 sio_write(port, 0x24, tmp);
375 }
376 msg_pdbg("Serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
377 /* LDN 0x7, reg 0x64/0x65 */
378 sio_write(port, 0x07, 0x7);
379 flashport = sio_read(port, 0x64) << 8;
380 flashport |= sio_read(port, 0x65);
381 msg_pdbg("Serial flash port 0x%04x\n", flashport);
382 /* Non-default port requested? */
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000383 param = extract_programmer_param("it87spiport");
384 if (param) {
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000385 char *endptr = NULL;
386 unsigned long forced_flashport;
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000387 forced_flashport = strtoul(param, &endptr, 0);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000388 /* Port 0, port >0x1000, unaligned ports and garbage strings
389 * are rejected.
Carl-Daniel Hailfinger01f3ef42010-03-25 02:50:40 +0000390 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000391 if (!forced_flashport || (forced_flashport >= 0x1000) ||
392 (forced_flashport & 0x7) || (*endptr != '\0')) {
393 /* Using ports below 0x100 is a really bad idea, and
394 * should only be done if no port between 0x100 and
395 * 0xff8 works due to routing issues.
396 */
397 msg_perr("Error: it87spiport specified, but no valid "
398 "port specified.\nPort must be a multiple of "
399 "0x8 and lie between 0x100 and 0xff8.\n");
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000400 exit_conf_mode_ite(port);
401 free(param);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000402 return 1;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000403 } else {
404 flashport = (uint16_t)forced_flashport;
405 msg_pinfo("Forcing serial flash port 0x%04x\n",
406 flashport);
407 sio_write(port, 0x64, (flashport >> 8));
408 sio_write(port, 0x65, (flashport & 0xff));
Carl-Daniel Hailfingerbb297f72009-07-11 18:05:42 +0000409 }
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000410 }
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000411 free(param);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000412 exit_conf_mode_ite(port);
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100413
Angel Pons3bd47522021-06-07 12:33:53 +0200414 struct it8716f_spi_data *data = calloc(1, sizeof(*data));
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100415 if (!data) {
416 msg_perr("Unable to allocate space for extra SPI master data.\n");
417 return SPI_GENERIC_ERROR;
418 }
419
Edward O'Callaghanb2b45072020-11-17 18:38:15 +1100420 data->flashport = flashport;
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100421 data->fast_spi = 1;
Edward O'Callaghanf65b9de2020-11-17 18:33:45 +1100422
423 register_shutdown(it8716f_shutdown, data);
424
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000425 if (internal_buses_supported & BUS_SPI)
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000426 msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000427 /* FIXME: Add the SPI bus or replace the other buses with it? */
Nico Huber90739d12021-05-11 17:53:34 +0200428 register_spi_master(&spi_master_it87xx, data);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000429 return 0;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000430}
431
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000432int init_superio_ite(void)
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000433{
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +0000434 int i;
435 int ret = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000436
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000437 for (i = 0; i < superio_count; i++) {
438 if (superios[i].vendor != SUPERIO_VENDOR_ITE)
439 continue;
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000440
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000441 switch (superios[i].model) {
442 case 0x8500:
443 case 0x8502:
444 case 0x8510:
445 case 0x8511:
446 case 0x8512:
447 /* FIXME: This should be enabled, but we need a check
448 * for laptop whitelisting due to the amount of things
449 * which can go wrong if the EC firmware does not
450 * implement the interface we want.
451 */
452 //it85xx_spi_init(superios[i]);
453 break;
454 case 0x8705:
455 ret |= it8705f_write_enable(superios[i].port);
456 break;
457 case 0x8716:
458 case 0x8718:
459 case 0x8720:
Vadim Girlin4dd0f902013-08-24 12:18:17 +0000460 case 0x8728:
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000461 ret |= it87spi_probe(superios[i].port);
462 break;
463 default:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000464 msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",
465 superios[i].model);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000466 }
Carl-Daniel Hailfinger34cc6cc2009-06-28 10:57:58 +0000467 }
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000468 return ret;
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000469}
470
Edward O'Callaghan779045d2020-11-17 18:11:47 +1100471#endif /* defined(__i386__) || defined(__x86_64__) */