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Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000015 */
16
17/*
18 * Datasheet:
19 * - Name: Intel 82802AB/82802AC Firmware Hub (FWH)
20 * - URL: http://www.intel.com/design/chipsets/datashts/290658.htm
21 * - PDF: http://download.intel.com/design/chipsets/datashts/29065804.pdf
22 * - Order number: 290658-004
23 */
24
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000025#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000026#include "chipdrivers.h"
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000027
Sean Nelson28accc22010-03-19 18:47:06 +000028void print_status_82802ab(uint8_t status)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000029{
Sean Nelsoned479d22010-03-24 23:14:32 +000030 msg_cdbg("%s", status & 0x80 ? "Ready:" : "Busy:");
31 msg_cdbg("%s", status & 0x40 ? "BE SUSPEND:" : "BE RUN/FINISH:");
32 msg_cdbg("%s", status & 0x20 ? "BE ERROR:" : "BE OK:");
33 msg_cdbg("%s", status & 0x10 ? "PROG ERR:" : "PROG OK:");
34 msg_cdbg("%s", status & 0x8 ? "VP ERR:" : "VPP OK:");
35 msg_cdbg("%s", status & 0x4 ? "PROG SUSPEND:" : "PROG RUN/FINISH:");
36 msg_cdbg("%s", status & 0x2 ? "WP|TBL#|WP#,ABORT:" : "UNLOCK:");
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000037}
38
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000039int probe_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000040{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000041 chipaddr bios = flash->virtual_memory;
Uwe Hermann91f4afa2011-07-28 08:13:25 +000042 uint8_t id1, id2, flashcontent1, flashcontent2;
Carl-Daniel Hailfingera8cf3622014-08-08 08:33:01 +000043 int shifted = (flash->chip->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000044
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000045 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000046 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000047 programmer_delay(10);
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000048
49 /* Enter ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000050 chip_writeb(flash, 0x90, bios);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000051 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000052
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000053 id1 = chip_readb(flash, bios + (0x00 << shifted));
54 id2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000055
56 /* Leave ID mode */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000057 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000058
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +000059 programmer_delay(10);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000060
Sean Nelsoned479d22010-03-24 23:14:32 +000061 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, id1, id2);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000062
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000063 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +000064 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000065
Uwe Hermann91f4afa2011-07-28 08:13:25 +000066 /*
67 * Read the product ID location again. We should now see normal
68 * flash contents.
69 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000070 flashcontent1 = chip_readb(flash, bios + (0x00 << shifted));
71 flashcontent2 = chip_readb(flash, bios + (0x01 << shifted));
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000072
73 if (id1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +000074 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000075 if (id2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +000076 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger12aa0be2010-03-22 23:47:38 +000077
Sean Nelsoned479d22010-03-24 23:14:32 +000078 msg_cdbg("\n");
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +000079 if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000080 return 0;
81
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000082 return 1;
83}
84
Stefan Tauner4404f732013-09-12 08:28:56 +000085/* FIXME: needs timeout */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000086uint8_t wait_82802ab(struct flashctx *flash)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000087{
88 uint8_t status;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +000089 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000090
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000091 chip_writeb(flash, 0x70, bios);
Angel Ponscc71eb52020-01-31 11:16:42 +010092
93 while ((chip_readb(flash, bios) & 0x80) == 0) // it's busy
94 ;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000095
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000096 status = chip_readb(flash, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +000097
Carl-Daniel Hailfinger4e9cebb2009-09-05 01:16:30 +000098 /* Reset to get a clean state */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000099 chip_writeb(flash, 0xFF, bios);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000100
101 return status;
102}
103
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000104int erase_block_82802ab(struct flashctx *flash, unsigned int page,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000105 unsigned int pagesize)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000106{
Sean Nelson54596372010-01-09 05:30:14 +0000107 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000108 uint8_t status;
109
110 // clear status register
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000111 chip_writeb(flash, 0x50, bios + page);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000112
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000113 // now start it
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000114 chip_writeb(flash, 0x20, bios + page);
115 chip_writeb(flash, 0xd0, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000116 programmer_delay(10);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000117
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000118 // now let's see what the register is
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000119 status = wait_82802ab(flash);
Sean Nelson28accc22010-03-19 18:47:06 +0000120 print_status_82802ab(status);
Stefan Reinauerab044b22009-09-16 08:26:59 +0000121
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000122 /* FIXME: Check the status register for errors. */
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000123 return 0;
124}
125
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000126/* chunksize is 1 */
Mark Marshallf20b7be2014-05-09 21:16:21 +0000127int write_82802ab(struct flashctx *flash, const uint8_t *src, unsigned int start, unsigned int len)
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000128{
Nico Huber519be662018-12-23 20:03:35 +0100129 unsigned int i;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000130 chipaddr dst = flash->virtual_memory + start;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000131
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000132 for (i = 0; i < len; i++) {
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000133 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000134 chip_writeb(flash, 0x40, dst);
135 chip_writeb(flash, *src++, dst++);
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000136 wait_82802ab(flash);
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000137 }
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000138
139 /* FIXME: Ignore errors for now. */
140 return 0;
Carl-Daniel Hailfingere7bcb192008-03-14 00:02:25 +0000141}
142
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000143int unlock_28f004s5(struct flashctx *flash)
Sean Nelsondee4a832010-03-22 04:39:31 +0000144{
145 chipaddr bios = flash->virtual_memory;
Sean Nelson4e54de92010-03-22 07:03:26 +0000146 uint8_t mcfg, bcfg, need_unlock = 0, can_unlock = 0;
Nico Huber519be662018-12-23 20:03:35 +0100147 unsigned int i;
Sean Nelsondee4a832010-03-22 04:39:31 +0000148
149 /* Clear status register */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000150 chip_writeb(flash, 0x50, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000151
152 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000153 chip_writeb(flash, 0x90, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000154
155 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000156 mcfg = chip_readb(flash, bios + 0x3);
Sean Nelsoned479d22010-03-24 23:14:32 +0000157 msg_cdbg("master lock is ");
Sean Nelsondee4a832010-03-22 04:39:31 +0000158 if (mcfg) {
159 msg_cdbg("locked!\n");
160 } else {
161 msg_cdbg("unlocked!\n");
162 can_unlock = 1;
163 }
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000164
Sean Nelsondee4a832010-03-22 04:39:31 +0000165 /* Read block lock-bits */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000166 for (i = 0; i < flash->chip->total_size * 1024; i+= (64 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000167 bcfg = chip_readb(flash, bios + i + 2); // read block lock config
Sean Nelsondee4a832010-03-22 04:39:31 +0000168 msg_cdbg("block lock at %06x is %slocked!\n", i, bcfg ? "" : "un");
169 if (bcfg) {
170 need_unlock = 1;
171 }
172 }
173
174 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000175 chip_writeb(flash, 0xFF, bios);
Sean Nelsondee4a832010-03-22 04:39:31 +0000176
177 /* Unlock: clear block lock-bits, if needed */
178 if (can_unlock && need_unlock) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000179 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000180 chip_writeb(flash, 0x60, bios);
181 chip_writeb(flash, 0xD0, bios);
182 chip_writeb(flash, 0xFF, bios);
Sean Nelsoned479d22010-03-24 23:14:32 +0000183 msg_cdbg("Done!\n");
Sean Nelsondee4a832010-03-22 04:39:31 +0000184 }
185
186 /* Error: master locked or a block is locked */
187 if (!can_unlock && need_unlock) {
188 msg_cerr("At least one block is locked and lockdown is active!\n");
189 return -1;
190 }
191
192 return 0;
193}
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000194
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000195int unlock_lh28f008bjt(struct flashctx *flash)
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000196{
197 chipaddr bios = flash->virtual_memory;
198 uint8_t mcfg, bcfg;
199 uint8_t need_unlock = 0, can_unlock = 0;
Nico Huber519be662018-12-23 20:03:35 +0100200 unsigned int i;
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000201
202 /* Wait if chip is busy */
203 wait_82802ab(flash);
204
205 /* Read identifier codes */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000206 chip_writeb(flash, 0x90, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000207
208 /* Read master lock-bit */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000209 mcfg = chip_readb(flash, bios + 0x3);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000210 msg_cdbg("master lock is ");
211 if (mcfg) {
212 msg_cdbg("locked!\n");
213 } else {
214 msg_cdbg("unlocked!\n");
215 can_unlock = 1;
216 }
217
218 /* Read block lock-bits, 8 * 8 KB + 15 * 64 KB */
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +0000219 for (i = 0; i < flash->chip->total_size * 1024;
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000220 i += (i >= (64 * 1024) ? 64 * 1024 : 8 * 1024)) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000221 bcfg = chip_readb(flash, bios + i + 2); /* read block lock config */
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000222 msg_cdbg("block lock at %06x is %slocked!\n", i,
223 bcfg ? "" : "un");
224 if (bcfg)
225 need_unlock = 1;
226 }
227
228 /* Reset chip */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000229 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000230
231 /* Unlock: clear block lock-bits, if needed */
232 if (can_unlock && need_unlock) {
233 msg_cdbg("Unlock: ");
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000234 chip_writeb(flash, 0x60, bios);
235 chip_writeb(flash, 0xD0, bios);
236 chip_writeb(flash, 0xFF, bios);
Mattias Mattssonfca3b012011-08-25 22:44:11 +0000237 wait_82802ab(flash);
238 msg_cdbg("Done!\n");
239 }
240
241 /* Error: master locked or a block is locked */
242 if (!can_unlock && need_unlock) {
243 msg_cerr("At least one block is locked and lockdown is active!\n");
244 return -1;
245 }
246
247 return 0;
248}