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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000017 */
18
19/*
20 * Contains the board specific flash enables.
21 */
22
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000023#include <strings.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000024#include <string.h>
Stefan Taunerb4e06bd2012-08-20 00:24:22 +000025#include <stdlib.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000026#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000028#include "hwaccess.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000030#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000069/* Winbond W83697 documentation indicates that the index register has to be written for each access. */
Jacob Garberbeeb8bc2019-06-21 15:24:17 -060070static void sio_mask_alzheimer(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +000071{
72 uint8_t tmp;
73
74 OUTB(reg, port);
75 tmp = INB(port + 1) & ~mask;
76 OUTB(reg, port);
77 OUTB(tmp | (data & mask), port + 1);
78}
79
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000080/* Not used yet. */
81#if 0
82static int enable_flash_decode_superio(void)
83{
84 int ret;
85 uint8_t tmp;
86
87 switch (superio.vendor) {
88 case SUPERIO_VENDOR_NONE:
89 ret = -1;
90 break;
91 case SUPERIO_VENDOR_ITE:
92 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000093 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000094 tmp = sio_read(superio.port, 0x24);
95 tmp |= 0xfc;
96 sio_write(superio.port, 0x24, tmp);
97 exit_conf_mode_ite(superio.port);
98 ret = 0;
99 break;
100 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000101 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +0000102 ret = -1;
103 break;
104 }
105 return ret;
106}
107#endif
108
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000109/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000110 * SMSC FDC37B787: Raise GPIO50
111 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000112static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000113{
114 uint8_t id, val;
115
116 OUTB(0x55, port); /* enter conf mode */
117 id = sio_read(port, 0x20);
118 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000119 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000120 OUTB(0xAA, port); /* leave conf mode */
121 return -1;
122 }
123
124 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
125
126 val = sio_read(port, 0xC8); /* GP50 */
127 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
128 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000129 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000130 OUTB(0xAA, port);
131 return -1;
132 }
133
134 sio_mask(port, 0xF9, 0x01, 0x01);
135
136 OUTB(0xAA, port); /* Leave conf mode */
137 return 0;
138}
139
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000140/*
141 * Suited for:
142 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000143 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000144static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000145{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000146 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000147}
148
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000149struct winbond_mux {
150 uint8_t reg; /* 0 if the corresponding pin is not muxed */
151 uint8_t data; /* reg/data/mask may be directly ... */
152 uint8_t mask; /* ... passed to sio_mask */
153};
154
155struct winbond_port {
156 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
157 uint8_t ldn; /* LDN this GPIO register is located in */
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200158 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000159 the GPIO port */
160 uint8_t base; /* base register in that LDN for the port */
161};
162
163struct winbond_chip {
164 uint8_t device_id; /* reg 0x20 of the expected w83626x */
165 uint8_t gpio_port_count;
166 const struct winbond_port *port;
167};
168
169
170#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
171
172enum winbond_id {
173 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000174 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000175 WINBOND_W83627THF_ID = 0x82,
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000176 WINBOND_W83697HF_ID = 0x60,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000177};
178
179static const struct winbond_mux w83627hf_port2_mux[8] = {
180 {0x2A, 0x01, 0x01}, /* or MIDI */
181 {0x2B, 0x80, 0x80}, /* or SPI */
182 {0x2B, 0x40, 0x40}, /* or SPI */
183 {0x2B, 0x20, 0x20}, /* or power LED */
184 {0x2B, 0x10, 0x10}, /* or watchdog */
185 {0x2B, 0x08, 0x08}, /* or infra red */
186 {0x2B, 0x04, 0x04}, /* or infra red */
187 {0x2B, 0x03, 0x03} /* or IRQ1 input */
188};
189
190static const struct winbond_port w83627hf[3] = {
191 UNIMPLEMENTED_PORT,
192 {w83627hf_port2_mux, 0x08, 0, 0xF0},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000193 UNIMPLEMENTED_PORT,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000194};
195
Michael Karcherea36c9c2010-06-27 15:07:52 +0000196static const struct winbond_mux w83627ehf_port2_mux[8] = {
197 {0x29, 0x06, 0x02}, /* or MIDI */
198 {0x29, 0x06, 0x02},
199 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
200 {0x24, 0x02, 0x00},
201 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
202 {0x2A, 0x01, 0x01},
203 {0x2A, 0x01, 0x01},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000204 {0x2A, 0x01, 0x01},
Michael Karcherea36c9c2010-06-27 15:07:52 +0000205};
206
207static const struct winbond_port w83627ehf[6] = {
208 UNIMPLEMENTED_PORT,
209 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
210 UNIMPLEMENTED_PORT,
211 UNIMPLEMENTED_PORT,
212 UNIMPLEMENTED_PORT,
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000213 UNIMPLEMENTED_PORT,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000214};
215
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000216static const struct winbond_mux w83627thf_port4_mux[8] = {
217 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
218 {0x2D, 0x02, 0x02}, /* or resume reset */
219 {0x2D, 0x04, 0x04}, /* or S3 input */
220 {0x2D, 0x08, 0x08}, /* or PSON# */
221 {0x2D, 0x10, 0x10}, /* or PWROK */
222 {0x2D, 0x20, 0x20}, /* or suspend LED */
223 {0x2D, 0x40, 0x40}, /* or panel switch input */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000224 {0x2D, 0x80, 0x80}, /* or panel switch output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000225};
226
227static const struct winbond_port w83627thf[5] = {
228 UNIMPLEMENTED_PORT, /* GPIO1 */
229 UNIMPLEMENTED_PORT, /* GPIO2 */
230 UNIMPLEMENTED_PORT, /* GPIO3 */
231 {w83627thf_port4_mux, 0x09, 1, 0xF4},
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000232 UNIMPLEMENTED_PORT, /* GPIO5 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000233};
234
235static const struct winbond_chip winbond_chips[] = {
236 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000237 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
239};
240
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000241#define WINBOND_SUPERIO_PORT1 0x2e
242#define WINBOND_SUPERIO_PORT2 0x4e
243
244/* We don't really care about the hardware monitor, but it offers better (more specific) device ID info than
245 * the simple device ID in the normal configuration registers.
246 * Note: This function expects to be called while the Super I/O is in config mode.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000247 */
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000248static uint8_t w836xx_deviceid_hwmon(uint16_t sio_port)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000249{
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000250 uint16_t hwmport;
251 uint16_t hwm_vendorid;
252 uint8_t hwm_deviceid;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000253
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000254 sio_write(sio_port, 0x07, 0x0b); /* Select LDN 0xb (HWM). */
255 if ((sio_read(sio_port, 0x30) & (1 << 0)) != (1 << 0)) {
256 msg_pinfo("W836xx hardware monitor disabled or does not exist.\n");
257 return 0;
258 }
259 /* Get HWM base address (stored in LDN 0xb, index 0x60/0x61). */
260 hwmport = sio_read(sio_port, 0x60) << 8;
261 hwmport |= sio_read(sio_port, 0x61);
262 /* HWM address register = HWM base address + 5. */
263 hwmport += 5;
264 msg_pdbg2("W836xx Hardware Monitor at port %04x\n", hwmport);
265 /* FIXME: This busy check should happen before each HWM access. */
266 if (INB(hwmport) & 0x80) {
267 msg_pinfo("W836xx hardware monitor busy, ignoring it.\n");
268 return 0;
269 }
270 /* Set HBACS=1. */
271 sio_mask_alzheimer(hwmport, 0x4e, 0x80, 0x80);
272 /* Read upper byte of vendor ID. */
273 hwm_vendorid = sio_read(hwmport, 0x4f) << 8;
274 /* Set HBACS=0. */
275 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x80);
276 /* Read lower byte of vendor ID. */
277 hwm_vendorid |= sio_read(hwmport, 0x4f);
278 if (hwm_vendorid != 0x5ca3) {
279 msg_pinfo("W836xx hardware monitor vendor ID weirdness: expected 0x5ca3, got %04x\n",
280 hwm_vendorid);
281 return 0;
282 }
283 /* Set Bank=0. */
284 sio_mask_alzheimer(hwmport, 0x4e, 0x00, 0x07);
285 /* Read "chip" ID. We call this one the device ID. */
286 hwm_deviceid = sio_read(hwmport, 0x58);
287 return hwm_deviceid;
288}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000289
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000290void probe_superio_winbond(void)
291{
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +0000292 struct superio s = {0};
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000293 uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0};
294 uint16_t *i = winbond_ports;
295 uint8_t model;
296 uint8_t tmp;
297
298 s.vendor = SUPERIO_VENDOR_WINBOND;
299 for (; *i; i++) {
300 s.port = *i;
301 /* If we're already in Super I/O config more, the W836xx enter sequence won't hurt. */
302 w836xx_ext_enter(s.port);
303 model = sio_read(s.port, 0x20);
304 /* No response, no point leaving the config mode. */
305 if (model == 0xff)
306 continue;
307 /* Try to leave config mode. If the ID register is still readable, it's not a Winbond chip. */
308 w836xx_ext_leave(s.port);
309 if (model == sio_read(s.port, 0x20)) {
310 msg_pdbg("W836xx enter config mode worked or we were already in config mode. W836xx "
311 "leave config mode had no effect.\n");
312 if (model == 0x87) {
313 /* ITE IT8707F and IT8710F are special: They need the W837xx enter sequence,
314 * but they want the ITE exit sequence. Handle them here.
315 */
316 tmp = sio_read(s.port, 0x21);
317 switch (tmp) {
318 case 0x07:
319 case 0x10:
320 s.vendor = SUPERIO_VENDOR_ITE;
321 s.model = (0x87 << 8) | tmp ;
322 msg_pdbg("Found ITE Super I/O, ID 0x%04hx on port "
323 "0x%x\n", s.model, s.port);
324 register_superio(s);
325 /* Exit ITE config mode. */
326 exit_conf_mode_ite(s.port);
327 /* Restore vendor for next loop iteration. */
328 s.vendor = SUPERIO_VENDOR_WINBOND;
329 continue;
330 }
331 }
Stefan Tauner23e10b82016-01-23 16:16:49 +0000332 msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000333 continue;
Stefan Tauner23e10b82016-01-23 16:16:49 +0000334 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000335 /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */
336 w836xx_ext_enter(s.port);
337 s.model = sio_read(s.port, 0x20);
338 switch (s.model) {
339 case WINBOND_W83627HF_ID:
340 case WINBOND_W83627EHF_ID:
341 case WINBOND_W83627THF_ID:
Stefan Taunereb582572012-09-21 12:52:50 +0000342 msg_pdbg("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000343 register_superio(s);
344 break;
345 case WINBOND_W83697HF_ID:
346 /* This code is extremely paranoid. */
347 tmp = sio_read(s.port, 0x26) & 0x40;
348 if (((tmp == 0x00) && (s.port != WINBOND_SUPERIO_PORT1)) ||
349 ((tmp == 0x40) && (s.port != WINBOND_SUPERIO_PORT2))) {
350 msg_pdbg("Winbond Super I/O probe weirdness: Port mismatch for ID "
Stefan Taunereb582572012-09-21 12:52:50 +0000351 "0x%02x at port 0x%04x\n", s.model, s.port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000352 break;
353 }
354 tmp = w836xx_deviceid_hwmon(s.port);
355 /* FIXME: This might be too paranoid... */
356 if (!tmp) {
357 msg_pdbg("Probably not a Winbond Super I/O\n");
358 break;
359 }
360 if (tmp != s.model) {
Stefan Taunereb582572012-09-21 12:52:50 +0000361 msg_pinfo("W83 series hardware monitor device ID weirdness: expected 0x%02x, "
362 "got 0x%02x\n", WINBOND_W83697HF_ID, tmp);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000363 break;
364 }
Stefan Taunereb582572012-09-21 12:52:50 +0000365 msg_pinfo("Found Winbond Super I/O, id 0x%02hx\n", s.model);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000366 register_superio(s);
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000367 break;
368 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000369 w836xx_ext_leave(s.port);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000370 }
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000371 return;
372}
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000373
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000374static const struct winbond_chip *winbond_superio_chipdef(void)
375{
Nico Huber519be662018-12-23 20:03:35 +0100376 int i;
377 unsigned int j;
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000378
379 for (i = 0; i < superio_count; i++) {
380 if (superios[i].vendor != SUPERIO_VENDOR_WINBOND)
381 continue;
382 for (j = 0; j < ARRAY_SIZE(winbond_chips); j++)
383 if (winbond_chips[j].device_id == superios[i].model)
384 return &winbond_chips[j];
385 }
386 return NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000387}
388
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000389/*
390 * The chipid parameter goes away as soon as we have Super I/O matching in the
391 * board enable table. The call to winbond_superio_detect() goes away as
392 * soon as we have generic Super I/O detection code.
393 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000394static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
395 int pin, int raise)
396{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000397 const struct winbond_chip *chip = NULL;
398 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000399 int port = pin / 10;
400 int bit = pin % 10;
401
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000402 chip = winbond_superio_chipdef();
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000403 if (!chip) {
404 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
405 return -1;
406 }
Michael Karcher979d9252010-06-29 14:44:40 +0000407 if (chip->device_id != chipid) {
408 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
409 "expected %x\n", chip->device_id, chipid);
410 return -1;
411 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000412 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
413 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
414 pin);
415 return -1;
416 }
417
418 gpio = &chip->port[port - 1];
419
420 if (gpio->ldn == 0) {
421 msg_perr("\nERROR: GPIO%d is not supported yet on this"
422 " winbond chip\n", port);
423 return -1;
424 }
425
426 w836xx_ext_enter(base);
427
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000428 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000429 sio_write(base, 0x07, gpio->ldn);
430
431 /* Activate logical device. */
432 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
433
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000434 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000435 if (gpio->mux && gpio->mux[bit].reg)
436 sio_mask(base, gpio->mux[bit].reg,
437 gpio->mux[bit].data, gpio->mux[bit].mask);
438
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000439 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000440 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
441 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
442
443 w836xx_ext_leave(base);
444
445 return 0;
446}
447
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000448/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000449 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000450 *
451 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000452 * - Agami Aruma
453 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000454 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000455static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000456{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000457 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000458}
459
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000460/*
Joshua Roysf280a382010-08-07 21:49:11 +0000461 * Winbond W83627HF: Raise GPIO25.
462 *
463 * Suited for:
464 * - MSI MS-6577
465 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000466static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000467{
468 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
469}
470
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000471/*
Stefan Taunerff80e682011-07-20 16:34:18 +0000472 * Winbond W83627EHF: Raise GPIO22.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000473 *
474 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000475 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000476 */
Stefan Taunerff80e682011-07-20 16:34:18 +0000477static int w83627ehf_gpio22_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000478{
Stefan Taunerff80e682011-07-20 16:34:18 +0000479 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1);
Michael Karcherea36c9c2010-06-27 15:07:52 +0000480}
481
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000482/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000483 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000484 *
485 * Suited for:
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000486 * - MSI K8T Neo2-F V2.0
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000487 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000488static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000489{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000490 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000491}
492
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000493/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000494 * Winbond W83627THF: Raise GPIO 44.
495 *
496 * Suited for:
497 * - MSI K8N Neo3
498 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000499static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000500{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000501 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000502}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000503
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000504/*
David Borgb6417a62010-08-02 08:29:34 +0000505 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000506 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000507 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000508static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000509{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000510 w836xx_ext_enter(port);
511 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000512 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000513 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000514 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000515 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000516}
517
David Borgb02c62b2012-05-05 20:43:42 +0000518/**
519 * Enable MEMW# and set ROM size to max.
520 * Supported chips:
521 * W83697HF/F/HG, W83697SF/UF/UG
522 */
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600523static void w83697xx_memw_enable(uint16_t port)
David Borgb02c62b2012-05-05 20:43:42 +0000524{
525 w836xx_ext_enter(port);
526 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
527 if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
528
529 /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
530 /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200531 /* These bits are reserved on W83697HF/F/HG */
532 /* Shouldn't be needed though. */
David Borgb02c62b2012-05-05 20:43:42 +0000533
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200534 /* CR28 Bit3 must be set to 1 to enable flash access to */
David Borgb02c62b2012-05-05 20:43:42 +0000535 /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
536 /* This bit is reserved on W83697HF/F/HG which default to 0 */
537 sio_mask(port, 0x28, 0x08, 0x08);
538
539 /* Enable MEMW# and set ROM size select to max. (4M)*/
540 sio_mask(port, 0x24, 0x28, 0x38);
541
542 } else {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000543 msg_pwarn("Warning: Flash interface in use by GPIO!\n");
David Borgb02c62b2012-05-05 20:43:42 +0000544 }
545 } else {
546 msg_pinfo("BIOS ROM is disabled\n");
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200547 }
548 w836xx_ext_leave(port);
David Borgb02c62b2012-05-05 20:43:42 +0000549}
550
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000551/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000552 * Suited for:
Stefan Taunerb6304c12012-08-09 23:25:27 +0000553 * - Biostar M7VIQ: VIA KM266 + VT8235
554 */
555static int w83697xx_memw_enable_2e(void)
556{
557 w83697xx_memw_enable(0x2E);
558
559 return 0;
560}
561
562
563/*
564 * Suited for:
Tadas Slotkus3dcdc032012-08-25 03:53:12 +0000565 * - DFI AD77: VIA KT400 + VT8235 + W83697HF
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000566 * - EPoX EP-8K5A2: VIA KT333 + VT8235
567 * - Albatron PM266A Pro: VIA P4M266A + VT8235
568 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
569 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
570 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000571 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000572 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000573 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000574 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Pawel Rozanski1d233072011-06-19 16:52:48 +0000575 * - ASRock K7S41GX: SiS 741GX + SiS 963L + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000576 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000577static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000578{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000579 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000580
Luc Verhaegen73d21192009-12-23 00:54:26 +0000581 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000582}
583
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000584/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000585 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000586 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000587 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000588static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000589{
590 w836xx_memw_enable(0x4E);
591
592 return 0;
593}
594
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000595/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000596 * Suited for all boards with ITE IT8705F.
597 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000598 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000599int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000600{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000601 uint8_t tmp;
602 int ret = 0;
603
Nico Huber2e50cdc2018-09-23 20:20:26 +0200604 if (!(internal_buses_supported & BUS_PARALLEL))
605 return 1;
606
Luc Verhaegen21f54962010-01-20 14:45:07 +0000607 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000608 tmp = sio_read(port, 0x24);
609 /* Check if at least one flash segment is enabled. */
610 if (tmp & 0xf0) {
611 /* The IT8705F will respond to LPC cycles and translate them. */
Nico Huber2e50cdc2018-09-23 20:20:26 +0200612 internal_buses_supported &= BUS_PARALLEL;
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000613 /* Flash ROM I/F Writes Enable */
614 tmp |= 0x04;
615 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
616 if (tmp & 0x02) {
617 /* The data sheet contradicts itself about max size. */
618 max_rom_decode.parallel = 1024 * 1024;
Stefan Taunerc2eec2c2014-05-03 21:33:01 +0000619 msg_pinfo("IT8705F with very unusual settings.\n"
620 "Please send the output of \"flashrom -V -p internal\" to flashrom@flashrom.org\n"
621 "with \"IT8705: your board name: flashrom -V\" as the subject to help us finish\n"
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000622 "support for your Super I/O. Thanks.\n");
623 ret = 1;
624 } else if (tmp & 0x08) {
625 max_rom_decode.parallel = 512 * 1024;
626 } else {
627 max_rom_decode.parallel = 256 * 1024;
628 }
629 /* Safety checks. The data sheet is unclear here: Segments 1+3
630 * overlap, no segment seems to cover top - 1MB to top - 512kB.
631 * We assume that certain combinations make no sense.
632 */
633 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
634 (!(tmp & 0x10)) || /* 128 kB dis */
635 (!(tmp & 0x40))) { /* 256/512 kB dis */
636 msg_perr("Inconsistent IT8705F decode size!\n");
637 ret = 1;
638 }
639 if (sio_read(port, 0x25) != 0) {
640 msg_perr("IT8705F flash data pins disabled!\n");
641 ret = 1;
642 }
643 if (sio_read(port, 0x26) != 0) {
644 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
645 ret = 1;
646 }
647 if (sio_read(port, 0x27) != 0) {
648 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
649 ret = 1;
650 }
651 if ((sio_read(port, 0x29) & 0x10) != 0) {
652 msg_perr("IT8705F flash write enable pin disabled!\n");
653 ret = 1;
654 }
655 if ((sio_read(port, 0x29) & 0x08) != 0) {
656 msg_perr("IT8705F flash chip select pin disabled!\n");
657 ret = 1;
658 }
659 if ((sio_read(port, 0x29) & 0x04) != 0) {
660 msg_perr("IT8705F flash read strobe pin disabled!\n");
661 ret = 1;
662 }
663 if ((sio_read(port, 0x29) & 0x03) != 0) {
664 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
665 /* Not really an error if you use flash chips smaller
666 * than 256 kByte, but such a configuration is unlikely.
667 */
668 ret = 1;
669 }
670 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
671 max_rom_decode.parallel);
672 if (ret) {
673 msg_pinfo("Not enabling IT8705F flash write.\n");
674 } else {
675 sio_write(port, 0x24, tmp);
676 }
677 } else {
678 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000679 ret = 0;
680 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000681 exit_conf_mode_ite(port);
682
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000683 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000684}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000685
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000686/*
687 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
688 * It uses the Winbond command sequence to enter extended configuration
689 * mode and the ITE sequence to exit.
690 *
691 * Registers seems similar to the ones on ITE IT8710F.
692 */
693static int it8707f_write_enable(uint8_t port)
694{
695 uint8_t tmp;
696
697 w836xx_ext_enter(port);
698
699 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
700 tmp = sio_read(port, 0x23);
701 tmp |= (1 << 3);
702 sio_write(port, 0x23, tmp);
703
704 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
705 tmp = sio_read(port, 0x24);
706 tmp |= (1 << 2) | (1 << 3);
707 sio_write(port, 0x24, tmp);
708
709 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
710 tmp = sio_read(port, 0x23);
711 tmp &= ~(1 << 3);
712 sio_write(port, 0x23, tmp);
713
714 exit_conf_mode_ite(port);
715
716 return 0;
717}
718
719/*
720 * Suited for:
721 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
722 */
723static int it8707f_write_enable_2e(void)
724{
725 return it8707f_write_enable(0x2e);
726}
727
Michael Karchercba52de2011-03-06 12:07:19 +0000728#define PC87360_ID 0xE1
729#define PC87364_ID 0xE4
730
731static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000732{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000733 static const int bankbase[] = {0, 4, 8, 10, 12};
734 int gpio_bank = gpio / 8;
735 int gpio_pin = gpio % 8;
736 uint16_t baseport;
737 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000738
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000739 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000740 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000741 return -1;
742 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000743
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000744 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000745 if (id != chipid) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000746 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n",
747 id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000748 return -1;
749 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000750
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000751 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
752 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
753 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
754 msg_perr("PC87360: invalid GPIO base address %04x\n",
755 baseport);
756 return -1;
757 }
758 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
759 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
760 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000761
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000762 val = INB(baseport + bankbase[gpio_bank]);
763 if (raise)
764 val |= 1 << gpio_pin;
765 else
766 val &= ~(1 << gpio_pin);
767 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000768
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000769 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000770}
771
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000772/*
773 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000774 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000775static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000776{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000777 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000778 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000779 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000780
Luc Verhaegen73d21192009-12-23 00:54:26 +0000781 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
782 switch (dev->device_id) {
783 case 0x3177: /* VT8235 */
Helge Wagnerdd73d832012-08-24 23:03:46 +0000784 case 0x3227: /* VT8237/VT8237R */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000785 case 0x3337: /* VT8237A */
786 break;
787 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000788 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000789 return -1;
790 }
791
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000792 if ((gpio >= 12) && (gpio <= 15)) {
793 /* GPIO12-15 -> output */
794 val = pci_read_byte(dev, 0xE4);
795 val |= 0x10;
796 pci_write_byte(dev, 0xE4, val);
797 } else if (gpio == 9) {
798 /* GPIO9 -> Output */
799 val = pci_read_byte(dev, 0xE4);
800 val |= 0x20;
801 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000802 } else if (gpio == 5) {
803 val = pci_read_byte(dev, 0xE4);
804 val |= 0x01;
805 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000806 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000807 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000808 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000809 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000810 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000811
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000812 /* We need the I/O Base Address for this board's flash enable. */
813 base = pci_read_word(dev, 0x88) & 0xff80;
814
David Bartleyf58d3642009-12-09 07:53:01 +0000815 offset = 0x4C + gpio / 8;
816 bit = 0x01 << (gpio % 8);
817
818 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000819 if (raise)
820 val |= bit;
821 else
822 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000823 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000824
Uwe Hermanna7e05482007-05-09 10:17:44 +0000825 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000826}
827
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000828/*
829 * Suited for:
830 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000831 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000832static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000833{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000834 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
835 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000836}
837
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000838/*
839 * Suited for:
840 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000841 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000842static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000843{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000844 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000845}
846
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000847/*
848 * Suited for:
849 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000850 *
851 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
852 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000853 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000854static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000855{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000856 return via_vt823x_gpio_set(15, 1);
857}
858
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000859/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000860 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
861 *
862 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000863 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
864 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000865 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000866static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000867{
868 int ret;
869
870 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000871 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000872
Luc Verhaegen73d21192009-12-23 00:54:26 +0000873 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000874}
875
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000876/*
877 * Suited for:
Keith Huic7e9a6e2020-05-12 21:43:58 -0400878 * - ASUS P3B-F
879 *
880 * We are talking to a proprietary device on SMBus: the AS99127F which does
881 * much more than the Winbond W83781D it tries to be compatible with.
882 */
883static int board_asus_p3b_f(void)
884{
885 /*
886 * Find where the SMBus host is. ASUS sets it to 0xE800; coreboot sets it to 0x0F00.
887 */
888 struct pci_dev *dev;
889 uint16_t smbba;
890 uint8_t b;
891
892 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4, PM/SMBus function. */
893 if (!dev) {
894 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
895 return -1;
896 }
897
898 smbba = pci_read_word(dev, 0x90) & 0xfff0;
899
900 OUTB(0xFF, smbba); /* Clear previous SMBus status. */
901 OUTB(0x48 << 1, smbba + 4);
902 OUTB(0x80, smbba + 3);
903 OUTB(0x80, smbba + 5);
904 OUTB(0x48, smbba + 2);
905
906 /* Wait until SMBus transaction is complete. */
907 b = 0x1;
908 while (b & 0x01) {
909 b = INB(0x80);
910 b = INB(smbba);
911 }
912
913 /* Write failed if any status is set. */
914 if (b & 0x1e) {
915 msg_perr("Failed to write to device.\n");
916 return -1;
917 }
918
919 return 0;
920}
921
922/*
923 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000924 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000925 *
926 * This is rather nasty code, but there's no way to do this cleanly.
927 * We're basically talking to some unknown device on SMBus, my guess
928 * is that it is the Winbond W83781D that lives near the DIP BIOS.
929 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000930static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000931{
932 uint8_t tmp;
933 int i;
934
935#define ASUSP5A_LOOP 5000
936
Andriy Gapon65c1b862008-05-22 13:22:45 +0000937 OUTB(0x00, 0xE807);
938 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000939
Andriy Gapon65c1b862008-05-22 13:22:45 +0000940 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000941
942 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000943 OUTB(0xE1, 0xFF);
944 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000945 break;
946 }
947
948 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000949 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000950 return -1;
951 }
952
Andriy Gapon65c1b862008-05-22 13:22:45 +0000953 OUTB(0x20, 0xE801);
954 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000955
Andriy Gapon65c1b862008-05-22 13:22:45 +0000956 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000957
958 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000959 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000960 if (tmp & 0x70)
961 break;
962 }
963
964 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000965 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000966 return -1;
967 }
968
Andriy Gapon65c1b862008-05-22 13:22:45 +0000969 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000970 tmp &= ~0x02;
971
Andriy Gapon65c1b862008-05-22 13:22:45 +0000972 OUTB(0x00, 0xE807);
973 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000974
Andriy Gapon65c1b862008-05-22 13:22:45 +0000975 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000976
Andriy Gapon65c1b862008-05-22 13:22:45 +0000977 OUTB(0xFF, 0xE800);
978 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000979
Andriy Gapon65c1b862008-05-22 13:22:45 +0000980 OUTB(0x20, 0xE801);
981 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000982
Andriy Gapon65c1b862008-05-22 13:22:45 +0000983 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000984
985 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000986 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000987 if (tmp & 0x70)
988 break;
989 }
990
991 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000992 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000993 return -1;
994 }
995
996 return 0;
997}
998
Luc Verhaegena7e30502009-12-09 11:39:02 +0000999/*
1000 * Set GPIO lines in the Broadcom HT-1000 southbridge.
1001 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001002 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +00001003 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001004static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +00001005{
1006 /* GPIO 0 reg from PM regs */
1007 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
1008 sio_mask(0xcd6, 0x44, 0x24, 0x24);
1009
1010 return 0;
1011}
1012
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001013/*
1014 * Set GPIO lines in the Broadcom HT-1000 southbridge.
1015 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001016 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001017 */
1018static int board_hp_dl165_g6_enable(void)
1019{
1020 /* Variant of DL145, with slightly different pin placement. */
1021 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
1022 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
1023
1024 return 0;
1025}
1026
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001027static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +00001028{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001029 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +00001030 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +00001031
1032 return 0;
1033}
1034
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001035/*
1036 * Suited for:
Mattias Mattssonf4925162010-09-16 22:09:18 +00001037 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
1038 */
Mattias Mattssonf4925162010-09-16 22:09:18 +00001039static int board_ecs_geforce6100sm_m(void)
1040{
1041 struct pci_dev *dev;
1042 uint32_t tmp;
1043
1044 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
1045 if (!dev) {
1046 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
1047 return -1;
1048 }
1049
1050 tmp = pci_read_byte(dev, 0xE0);
1051 tmp &= ~(1 << 3);
1052 pci_write_byte(dev, 0xE0, tmp);
1053
1054 return 0;
1055}
1056
1057/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001058 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001059 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001060static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001061{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001062 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001063 uint16_t base, devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001064 uint8_t tmp;
1065
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001066 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001067 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001068 return -1;
1069 }
1070
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001071 /* Check for the ISA bridge first. */
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001072 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001073 switch (dev->device_id) {
1074 case 0x0030: /* CK804 */
1075 case 0x0050: /* MCP04 */
1076 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001077 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001078 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001079 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +00001080 case 0x0261: /* MCP51 */
Joshua Roys6e48a022012-06-29 23:07:14 +00001081 case 0x0360: /* MCP55 */
Michael Karcher2ead2e22010-06-01 16:09:06 +00001082 case 0x0364: /* MCP55 */
1083 /* find SMBus controller on *this* southbridge */
1084 /* The infamous Tyan S2915-E has two south bridges; they are
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001085 easily told apart from each other by the class of the
Michael Karcher2ead2e22010-06-01 16:09:06 +00001086 LPC bridge, but have the same SMBus bridge IDs */
1087 if (dev->func != 0) {
1088 msg_perr("MCP LPC bridge at unexpected function"
1089 " number %d\n", dev->func);
1090 return -1;
1091 }
1092
Stefan Tauner56734502015-02-08 21:58:04 +00001093#if !defined(OLD_PCI_GET_DEV)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001094 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +00001095#else
1096 /* pciutils/libpci before version 2.2 is too old to support
1097 * PCI domains. Such old machines usually don't have domains
1098 * besides domain 0, so this is not a problem.
1099 */
1100 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
1101#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +00001102 if (!dev) {
1103 msg_perr("MCP SMBus controller could not be found\n");
1104 return -1;
1105 }
1106 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
1107 if (devclass != 0x0C05) {
1108 msg_perr("Unexpected device class %04x for SMBus"
1109 " controller\n", devclass);
1110 return -1;
1111 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +00001112 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +00001113 default:
Sean Nelson316a29f2010-05-07 20:09:04 +00001114 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001115 return -1;
1116 }
1117
1118 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
1119 base += 0xC0;
1120
1121 tmp = INB(base + gpio);
1122 tmp &= ~0x0F; /* null lower nibble */
1123 tmp |= 0x04; /* gpio -> output. */
1124 if (raise)
1125 tmp |= 0x01;
1126 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +00001127
1128 return 0;
1129}
1130
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001131/*
1132 * Suited for:
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001133 * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51
Sean Nelson0a247512010-08-15 14:36:18 +00001134 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001135 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +00001136 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001137static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +00001138{
1139 return nvidia_mcp_gpio_set(0x00, 1);
1140}
1141
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001142/*
1143 * Suited for:
1144 * - abit KN8 Ultra: NVIDIA CK804
Stefan Tauner74dc73f2015-03-01 22:04:38 +00001145 * - abit KN9 Ultra: NVIDIA MCP55
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001146 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001147static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001148{
1149 return nvidia_mcp_gpio_set(0x02, 0);
1150}
1151
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001152/*
1153 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +00001154 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001155 * - MSI K8N Neo4(-F/-FI/-FX/Platinum): NVIDIA CK804
Uwe Hermannead705f2010-08-15 15:26:30 +00001156 * - MSI K8NGM2-L: NVIDIA MCP51
Joshua Roys6e48a022012-06-29 23:07:14 +00001157 * - MSI K9N SLI: NVIDIA MCP55
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001158 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001159static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +00001160{
1161 return nvidia_mcp_gpio_set(0x02, 1);
1162}
1163
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001164/*
1165 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +00001166 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +00001167 */
1168static int nvidia_mcp_gpio4_raise(void)
1169{
1170 return nvidia_mcp_gpio_set(0x04, 1);
1171}
1172
1173/*
1174 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001175 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
1176 *
1177 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
1178 * board. We can't tell the SMBus logical devices apart, but we
1179 * can tell the LPC bridge functions apart.
1180 * We need to choose the SMBus bridge next to the LPC bridge with
1181 * ID 0x364 and the "LPC bridge" class.
1182 * b) #TBL is hardwired on that board to a pull-down. It can be
1183 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +00001184 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001185static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +00001186{
1187 return nvidia_mcp_gpio_set(0x05, 1);
1188}
1189
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001190/*
1191 * Suited for:
1192 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +00001193 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001194static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +00001195{
1196 return nvidia_mcp_gpio_set(0x08, 1);
1197}
1198
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001199/*
1200 * Suited for:
Cristian Măgherușan-Stanciu9932c7b2011-07-07 19:56:58 +00001201 * - GIGABYTE GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
Stefan Tauner23e10b82016-01-23 16:16:49 +00001202 * - Probably other versions of the GA-K8NS
Idwer Volleringd8a00a02011-06-13 16:58:54 +00001203 */
1204static int nvidia_mcp_gpio0a_raise(void)
1205{
1206 return nvidia_mcp_gpio_set(0x0a, 1);
1207}
1208
1209/*
1210 * Suited for:
Stefan Tauner33366a02012-09-15 15:51:09 +00001211 * - MSI K8N Neo Platinum: Socket 754 + nForce3 Ultra + CK8
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001212 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001213 */
Michael Karcher51825082010-06-12 23:14:03 +00001214static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001215{
1216 return nvidia_mcp_gpio_set(0x0c, 1);
1217}
1218
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001219/*
1220 * Suited for:
1221 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001222 */
1223static int nvidia_mcp_gpio4_lower(void)
1224{
1225 return nvidia_mcp_gpio_set(0x04, 0);
1226}
1227
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001228/*
1229 * Suited for:
1230 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001231 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001232static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001233{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001234 return nvidia_mcp_gpio_set(0x10, 1);
1235}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001236
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001237/*
1238 * Suited for:
1239 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001240 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001241static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001242{
1243 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001244}
1245
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001246/*
1247 * Suited for:
1248 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001249 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001250static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001251{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001252 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001253}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001254
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001255/*
1256 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001257 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1258 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001259 */
1260static int nvidia_mcp_gpio3b_raise(void)
1261{
1262 return nvidia_mcp_gpio_set(0x3b, 1);
1263}
1264
1265/*
1266 * Suited for:
Joshua Roysb992d342011-11-02 14:31:18 +00001267 * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55
1268 */
1269static int board_sun_ultra_40_m2(void)
1270{
1271 int ret;
1272 uint8_t reg;
1273 uint16_t base;
1274 struct pci_dev *dev;
1275
1276 ret = nvidia_mcp_gpio4_lower();
1277 if (ret)
1278 return ret;
1279
1280 dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */
1281 if (!dev) {
1282 msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n");
1283 return -1;
1284 }
1285
1286 base = pci_read_word(dev, 0xb4); /* some IO BAR? */
1287 if (!base)
1288 return -1;
1289
1290 reg = INB(base + 0x4b);
1291 reg |= 0x10;
1292 OUTB(reg, base + 0x4b);
1293
1294 return 0;
1295}
1296
1297/*
1298 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001299 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001300 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001301static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001302{
1303#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001304#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1305#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1306#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001307#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1308#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1309#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001310#define DBE6x_BOOT_LOC_FLASH 2
1311#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001312
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001313 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001314 unsigned long boot_loc;
1315
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001316 /* Geode only has a single core */
1317 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001318 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001319
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001320 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001321
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001322 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001323 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1324 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1325 else
1326 boot_loc = DBE6x_BOOT_LOC_FLASH;
1327
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001328 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1329 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001330 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001331
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001332 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001333
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001334 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001335
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001336 return 0;
1337}
1338
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001339/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001340 * Suited for:
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001341 * - ASUS A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001342 * Datasheet(s) used:
1343 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1344 */
1345static int amd_sbxxx_gpio9_raise(void)
1346{
1347 struct pci_dev *dev;
1348 uint32_t reg;
1349
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001350 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus controller */
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001351 if (!dev) {
1352 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1353 return -1;
1354 }
1355
1356 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1357 /* enable output (0: enable, 1: tristate):
1358 GPIO9 output enable is at bit 5 in 0xA9 */
1359 reg &= ~((uint32_t)1<<(8+5));
1360 /* raise:
1361 GPIO9 output register is at bit 5 in 0xA8 */
1362 reg |= (1<<5);
1363 pci_write_long(dev, 0xA8, reg);
1364
1365 return 0;
1366}
1367
1368/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001369 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001370 */
1371static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1372{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001373 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001374 struct pci_dev *dev;
1375 uint32_t tmp, base;
1376
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001377 /* GPO{0,8,27,28,30} are always available. */
1378 static const uint32_t nonmuxed_gpos = 0x58000101;
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001379
1380 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001381 {0},
1382 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1383 {0xB0, 0x0001, 0x0000},
1384 {0xB0, 0x0001, 0x0000},
1385 {0xB0, 0x0001, 0x0000},
1386 {0xB0, 0x0001, 0x0000},
1387 {0xB0, 0x0001, 0x0000},
1388 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1389 {0},
1390 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1391 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1392 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1393 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1394 {0x4E, 0x0100, 0x0000},
1395 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1396 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1397 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1398 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1399 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1400 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1401 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1402 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1403 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1404 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1405 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1406 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1407 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1408 {0},
1409 {0},
1410 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1411 {0}
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001412 };
1413
Luc Verhaegenf5226912009-12-14 10:41:58 +00001414 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1415 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001416 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001417 return -1;
1418 }
1419
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001420 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001421 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001422 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001423 return -1;
1424 }
1425
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001426 if ((((1 << gpo) & nonmuxed_gpos) == 0) &&
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001427 ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) !=
1428 piix4_gpo[gpo].value)) {
1429 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001430 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001431 }
1432
Luc Verhaegenf5226912009-12-14 10:41:58 +00001433 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1434 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001435 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001436 return -1;
1437 }
1438
1439 /* PM IO base */
1440 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1441
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001442 gpo_byte = gpo >> 3;
1443 gpo_bit = gpo & 7;
1444 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001445 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001446 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001447 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001448 tmp &= ~(0x01 << gpo_bit);
1449 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001450
1451 return 0;
1452}
1453
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001454/*
1455 * Suited for:
Joshua Roysd708fad2012-02-17 14:51:15 +00001456 * - ASUS OPLX-M
Mattias Mattsson85016b92010-09-01 01:21:34 +00001457 * - ASUS P2B-N
1458 */
1459static int intel_piix4_gpo18_lower(void)
1460{
1461 return intel_piix4_gpo_set(18, 0);
1462}
1463
1464/*
1465 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001466 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1467 */
1468static int intel_piix4_gpo14_raise(void)
1469{
1470 return intel_piix4_gpo_set(14, 1);
1471}
1472
1473/*
1474 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001475 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001476 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001477static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001478{
1479 return intel_piix4_gpo_set(22, 1);
1480}
1481
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001482/*
1483 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001484 * - abit BM6
1485 */
1486static int intel_piix4_gpo26_lower(void)
1487{
1488 return intel_piix4_gpo_set(26, 0);
1489}
1490
1491/*
1492 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001493 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001494 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001495static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001496{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001497 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001498}
1499
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001500/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001501 * Suited for:
1502 * - Dell OptiPlex GX1
1503 */
1504static int intel_piix4_gpo30_lower(void)
1505{
1506 return intel_piix4_gpo_set(30, 0);
1507}
1508
1509/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001510 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001511 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001512static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001513{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001514 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001515 static struct {
1516 uint16_t id;
1517 uint8_t base_reg;
1518 uint32_t bank0;
1519 uint32_t bank1;
1520 uint32_t bank2;
1521 } intel_ich_gpio_table[] = {
1522 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1523 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1524 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1525 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1526 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1527 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1528 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1529 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1530 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1531 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1532 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1533 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001534 {0x27B0, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GDH (ICH7 DH) */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001535 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1536 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1537 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1538 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1539 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1540 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1541 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1542 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1543 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1544 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1545 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1546 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1547 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1548 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1549 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1550 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1551 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1552 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1553 {0, 0, 0, 0, 0} /* end marker */
1554 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001555
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001556 struct pci_dev *dev;
1557 uint16_t base;
1558 uint32_t tmp;
1559 int i, allowed;
1560
1561 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001562 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001563 uint16_t device_class;
1564 /* libpci before version 2.2.4 does not store class info. */
1565 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001566 if ((dev->vendor_id == 0x8086) &&
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001567 (device_class == 0x0601)) { /* ISA bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001568 /* Is this device in our list? */
1569 for (i = 0; intel_ich_gpio_table[i].id; i++)
1570 if (dev->device_id == intel_ich_gpio_table[i].id)
1571 break;
1572
1573 if (intel_ich_gpio_table[i].id)
1574 break;
1575 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001576 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001577
Uwe Hermann93f66db2008-05-22 21:19:38 +00001578 if (!dev) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001579 msg_perr("\nERROR: No known Intel LPC bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001580 return -1;
1581 }
1582
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001583 /*
1584 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1585 * strapped to zero. From some mobile ICH9 version on, this becomes
1586 * 6:1. The mask below catches all.
1587 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001588 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001589
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001590 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001591 if (gpio < 32)
1592 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1593 else if (gpio < 64)
1594 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1595 else
1596 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1597
1598 if (!allowed) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001599 msg_perr("\nERROR: This Intel LPC bridge does not allow"
1600 " setting GPIO%02d\n", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001601 return -1;
1602 }
1603
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001604 msg_pdbg("\nIntel ICH LPC bridge: %sing GPIO%02d.\n",
1605 raise ? "Rais" : "Dropp", gpio);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001606
1607 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001608 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001609 tmp = INL(base);
1610 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1611 if ((gpio == 28) &&
1612 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1613 tmp |= 1 << 27;
1614 else
1615 tmp |= 1 << gpio;
1616 OUTL(tmp, base);
1617
1618 /* As soon as we are talking to ICH8 and above, this register
1619 decides whether we can set the gpio or not. */
1620 if (dev->device_id > 0x2800) {
1621 tmp = INL(base);
1622 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001623 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001624 " does not allow setting GPIO%02d\n",
1625 gpio);
1626 return -1;
1627 }
1628 }
1629
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001630 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001631 tmp = INL(base + 0x04);
1632 tmp &= ~(1 << gpio);
1633 OUTL(tmp, base + 0x04);
1634
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001635 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001636 tmp = INL(base + 0x0C);
1637 if (raise)
1638 tmp |= 1 << gpio;
1639 else
1640 tmp &= ~(1 << gpio);
1641 OUTL(tmp, base + 0x0C);
1642 } else if (gpio < 64) {
1643 gpio -= 32;
1644
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001645 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001646 tmp = INL(base + 0x30);
1647 tmp |= 1 << gpio;
1648 OUTL(tmp, base + 0x30);
1649
1650 /* As soon as we are talking to ICH8 and above, this register
1651 decides whether we can set the gpio or not. */
1652 if (dev->device_id > 0x2800) {
1653 tmp = INL(base + 30);
1654 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001655 msg_perr("\nERROR: This Intel LPC bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001656 " does not allow setting GPIO%02d\n",
1657 gpio + 32);
1658 return -1;
1659 }
1660 }
1661
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001662 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001663 tmp = INL(base + 0x34);
1664 tmp &= ~(1 << gpio);
1665 OUTL(tmp, base + 0x34);
1666
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001667 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001668 tmp = INL(base + 0x38);
1669 if (raise)
1670 tmp |= 1 << gpio;
1671 else
1672 tmp &= ~(1 << gpio);
1673 OUTL(tmp, base + 0x38);
1674 } else {
1675 gpio -= 64;
1676
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001677 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001678 tmp = INL(base + 0x40);
1679 tmp |= 1 << gpio;
1680 OUTL(tmp, base + 0x40);
1681
1682 tmp = INL(base + 40);
1683 if (!(tmp & (1 << gpio))) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001684 msg_perr("\nERROR: This Intel LPC bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001685 "not allow setting GPIO%02d\n", gpio + 64);
1686 return -1;
1687 }
1688
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001689 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001690 tmp = INL(base + 0x44);
1691 tmp &= ~(1 << gpio);
1692 OUTL(tmp, base + 0x44);
1693
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001694 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001695 tmp = INL(base + 0x48);
1696 if (raise)
1697 tmp |= 1 << gpio;
1698 else
1699 tmp &= ~(1 << gpio);
1700 OUTL(tmp, base + 0x48);
1701 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001702
1703 return 0;
1704}
1705
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001706/*
1707 * Suited for:
1708 * - abit IP35: Intel P35 + ICH9R
1709 * - abit IP35 Pro: Intel P35 + ICH9R
Joshua Roysac8b2a12011-08-11 04:21:34 +00001710 * - ASUS P5LD2
Dima Veselov9d8f53d2014-07-14 18:04:15 +00001711 * - ASUS P5LD2-MQ
Idwer Vollering4d0cde12012-09-07 08:27:46 +00001712 * - ASUS P5LD2-VM
Stefan Tauner309dd2c2013-11-21 15:59:52 +00001713 * - ASUS P5LD2-VM DH
Uwe Hermann93f66db2008-05-22 21:19:38 +00001714 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001715static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001716{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001717 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001718}
1719
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001720/*
1721 * Suited for:
1722 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001723 */
1724static int intel_ich_gpio18_raise(void)
1725{
1726 return intel_ich_gpio_set(18, 1);
1727}
1728
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001729/*
1730 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001731 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001732 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001733static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001734{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001735 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001736}
1737
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001738/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001739 * Suited for:
Stefan Tauner027e0182012-05-02 19:48:21 +00001740 * - ASUS P5BV-R: LGA775 + 3200 + ICH7
Luc Verhaegen3f7e3412018-03-28 12:31:22 +02001741 * - AOpen i965GMt-LA: Intel Socket479 + 965GM + ICH8M
Stefan Tauner027e0182012-05-02 19:48:21 +00001742 */
1743static int intel_ich_gpio20_raise(void)
1744{
1745 return intel_ich_gpio_set(20, 1);
1746}
1747
1748/*
1749 * Suited for:
Stefan Taunereb582572012-09-21 12:52:50 +00001750 * - ASUS CUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001751 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1752 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001753 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001754 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001755 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Stefan Taunereb582572012-09-21 12:52:50 +00001756 * - ASUS P4P800-X: Intel socket478 + 865PE + ICH5R
Miklós Mártonde77ad42019-08-06 22:43:19 +02001757 * - ASUS P4P800SE: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001758 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roys1fd4f9e2011-08-11 05:47:32 +00001759 * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001760 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001761 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
Stefan Taunerded71e52012-03-10 19:22:13 +00001762 * - ASUS TUSL2-C: Intel socket370 + 815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001763 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001764 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001765static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001766{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001767 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001768}
1769
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001770/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001771 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001772 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001773 * - ASUS P4B533-E: socket478 + 845E + ICH4
1774 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Michael Karcherbfd89a52012-02-12 00:13:14 +00001775 * - TriGem Anaheim-3: socket370 + Intel 810 + ICH
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001776 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001777static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001778{
1779 return intel_ich_gpio_set(22, 1);
1780}
1781
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001782/*
1783 * Suited for:
Stefan Tauner716e0982011-07-25 20:38:52 +00001784 * - ASUS A8Jm (laptop): Intel 945 + ICH7
Michael Karcher14ab8d42011-08-25 14:06:50 +00001785 * - ASUS P5LP-LE used in ...
1786 * - HP Media Center m7270.fr Desktop PC as "Lithium-UL8E"
1787 * - Epson Endeavor MT7700
Stefan Tauner716e0982011-07-25 20:38:52 +00001788 */
1789static int intel_ich_gpio34_raise(void)
1790{
1791 return intel_ich_gpio_set(34, 1);
1792}
1793
1794/*
1795 * Suited for:
Stefan Taunerc6782182012-01-19 17:50:32 +00001796 * - AOpen i945GMx-VFX: Intel 945GM + ICH7-M used in ...
Paul Menzelac427b22012-02-16 21:07:07 +00001797 * - FSC ESPRIMO Q5010 (SMBIOS: D2544-B1)
Stefan Taunerc6782182012-01-19 17:50:32 +00001798 */
1799static int intel_ich_gpio38_raise(void)
1800{
1801 return intel_ich_gpio_set(38, 1);
1802}
1803
1804/*
1805 * Suited for:
Joshua Roysc73e2812011-07-09 19:46:53 +00001806 * - ASUS M6Ne (laptop): socket 479M (guessed) + Intel 855PM + ICH4-M
1807 */
1808static int intel_ich_gpio43_raise(void)
1809{
1810 return intel_ich_gpio_set(43, 1);
1811}
1812
1813/*
1814 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001815 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001816 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001817static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001818{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001819 int ret;
1820 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1821 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001822 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001823 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001824 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1825 return ret;
1826}
1827
1828/*
1829 * Suited for:
1830 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1831 */
1832static int board_hp_p2706t(void)
1833{
1834 int ret;
1835 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1836 if (!ret)
1837 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001838 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001839}
1840
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001841/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001842 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001843 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1844 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1845 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001846 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001847 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001848static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001849{
1850 return intel_ich_gpio_set(23, 1);
1851}
1852
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001853/*
1854 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001855 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001856 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001857 */
1858static int intel_ich_gpio25_raise(void)
1859{
1860 return intel_ich_gpio_set(25, 1);
1861}
1862
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001863/*
1864 * Suited for:
1865 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001866 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001867static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001868{
1869 return intel_ich_gpio_set(26, 1);
1870}
1871
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001872/*
1873 * Suited for:
Stefan Tauner98546c92012-11-05 12:20:29 +00001874 * - ASUS DSAN-DX
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001875 * - P4SD-LA (HP OEM): i865 + ICH5
Joshua Roys9d9a1042011-06-13 16:59:01 +00001876 * - GIGABYTE GA-8IP775: 865P + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001877 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001878 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001879 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001880static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001881{
1882 return intel_ich_gpio_set(32, 1);
1883}
1884
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001885/*
1886 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001887 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1888 */
1889static int board_aopen_i975xa_ydg(void)
1890{
1891 int ret;
1892
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001893 /* Vendor BIOS ends up in LDN6... maybe the board enable is wrong,
Joshua Roys7225ccd2011-05-18 01:32:16 +00001894 * or perhaps it's not needed at all?
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001895 * The regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1896 * were in the right LDN, it would have to be GPIO1 or GPIO3.
Joshua Roys7225ccd2011-05-18 01:32:16 +00001897 */
1898/*
1899 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1900 if (!ret)
1901*/
1902 ret = intel_ich_gpio_set(33, 1);
1903
1904 return ret;
1905}
1906
1907/*
1908 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001909 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001910 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001911static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001912{
1913 int ret;
1914
1915 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1916 ret = intel_ich_gpio_set(22, 1);
1917 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1918 ret = intel_ich_gpio_set(23, 1);
1919
1920 return ret;
1921}
1922
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001923/*
1924 * Suited for:
1925 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001926 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001927static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001928{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001929 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001930
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001931 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1932 if (!ret)
1933 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001934
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001935 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001936}
1937
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001938/*
1939 * Suited for:
1940 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001941 */
Michael Karcher06477332010-03-19 22:49:09 +00001942static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001943{
Michael Karcher06477332010-03-19 22:49:09 +00001944 struct pci_dev *dev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001945 uint32_t base, tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001946
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001947 /* VT82C686 power management */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001948 dev = pci_dev_find(0x1106, 0x3057);
1949 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001950 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001951 return -1;
1952 }
1953
Sean Nelson316a29f2010-05-07 20:09:04 +00001954 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001955 raise ? "Rais" : "Dropp", gpio);
Michael Karcher06477332010-03-19 22:49:09 +0000