blob: e04950a83a0f3634d1980c5bf039cbe96b33c29c [file] [log] [blame]
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 * Copyright (C) 2011 Jonathan Kollasch <jakllsch@kollasch.net>
6 * Copyright (C) 2012-2013 Stefan Tauner
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +000017 */
18
19#include <stdlib.h>
20#include <string.h>
21#include "flash.h"
22#include "programmer.h"
23#include "hwaccess.h"
24
25#define PCI_VENDOR_ID_VIA 0x1106
26
27#define VIA_MAX_RETRIES 300
28
29#define BROM_ADDR 0x60
30
31#define BROM_DATA 0x64
32
33#define BROM_ACCESS 0x68
34#define BROM_TRIGGER 0x80
35#define BROM_WRITE 0x40
36#define BROM_SIZE_MASK 0x30
37#define BROM_SIZE_64K 0x00
38#define BROM_SIZE_32K 0x10
39#define BROM_SIZE_16K 0x20
40#define BROM_SIZE_0K 0x30
41#define BROM_BYTE_ENABLE_MASK 0x0f
42
43#define BROM_STATUS 0x69
44#define BROM_ERROR_STATUS 0x80
45
46/* Select the byte we want to access. This is done by clearing the bit corresponding to the byte we want to
47 * access, leaving the others set (yes, really). */
48#define ENABLE_BYTE(address) ((~(1 << ((address) & 3))) & BROM_BYTE_ENABLE_MASK)
49#define BYTE_OFFSET(address) (((addr) & 3) * 8)
50
51const struct dev_entry ata_via[] = {
52 {PCI_VENDOR_ID_VIA, 0x3249, DEP, "VIA", "VT6421A"},
53
Evgeny Zinoviev83c56b82019-11-05 17:47:43 +030054 {0},
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +000055};
56
57static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
58static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000059static const struct par_master lpc_master_atavia = {
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +000060 .chip_readb = atavia_chip_readb,
61 .chip_readw = fallback_chip_readw,
62 .chip_readl = fallback_chip_readl,
63 .chip_readn = fallback_chip_readn,
64 .chip_writeb = atavia_chip_writeb,
65 .chip_writew = fallback_chip_writew,
66 .chip_writel = fallback_chip_writel,
67 .chip_writen = fallback_chip_writen,
68};
69
70static void *atavia_offset = NULL;
Stefan Tauner4f094752014-06-01 22:36:30 +000071static struct pci_dev *dev = NULL;
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +000072
73static void atavia_prettyprint_access(uint8_t access)
74{
75 uint8_t bmask = access & BROM_BYTE_ENABLE_MASK;
76 uint8_t size = access & BROM_SIZE_MASK;
77
78 msg_pspew("Accessing byte(s):%s%s%s%s\n",
79 ((bmask & (1<<3)) == 0) ? " 3" : "",
80 ((bmask & (1<<2)) == 0) ? " 2" : "",
81 ((bmask & (1<<1)) == 0) ? " 1" : "",
82 ((bmask & (1<<0)) == 0) ? " 0" : "");
83 if (size == BROM_SIZE_0K) {
84 msg_pspew("No ROM device found.\n");
85 } else
86 msg_pspew("ROM device with %s kB attached.\n",
87 (size == BROM_SIZE_64K) ? ">=64" :
88 (size == BROM_SIZE_32K) ? "32" : "16");
89 msg_pspew("Access is a %s.\n", (access & BROM_WRITE) ? "write" : "read");
90 msg_pspew("Device is %s.\n", (access & BROM_TRIGGER) ? "busy" : "ready");
91}
92
93static bool atavia_ready(struct pci_dev *pcidev_dev)
94{
95 int try;
96 uint8_t access, status;
97 bool ready = false;
98
99 for (try = 0; try < VIA_MAX_RETRIES; try++) {
100 access = pci_read_byte(pcidev_dev, BROM_ACCESS);
101 status = pci_read_byte(pcidev_dev, BROM_STATUS);
102 if (((access & BROM_TRIGGER) == 0) && (status & BROM_ERROR_STATUS) == 0) {
103 ready = true;
104 break;
105 } else {
106 programmer_delay(1);
107 continue;
108 }
109 }
110
111 msg_pdbg2("\n%s: %s after %d tries (access=0x%02x, status=0x%02x)\n",
Stefan Tauner6697f712014-08-06 15:09:15 +0000112 __func__, ready ? "succeeded" : "failed", try, access, status);
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000113 atavia_prettyprint_access(access);
114 return ready;
115}
116
Stefan Tauner4f094752014-06-01 22:36:30 +0000117void *atavia_map(const char *descr, uintptr_t phys_addr, size_t len)
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000118{
119 return (atavia_offset != 0) ? atavia_offset : (void *)phys_addr;
120}
121
122int atavia_init(void)
123{
124 char *arg = extract_programmer_param("offset");
125 if (arg) {
126 if (strlen(arg) == 0) {
127 msg_perr("Missing argument for offset.\n");
128 free(arg);
129 return ERROR_FATAL;
130 }
131 char *endptr;
132 atavia_offset = (void *)strtoul(arg, &endptr, 0);
133 if (*endptr) {
134 msg_perr("Error: Invalid offset specified: \"%s\".\n", arg);
135 free(arg);
136 return ERROR_FATAL;
137 }
138 msg_pinfo("Mapping addresses to base %p.\n", atavia_offset);
139 }
140 free(arg);
141
142 if (rget_io_perms())
143 return 1;
144
Carl-Daniel Hailfingere4c2b482020-01-20 11:22:41 +0100145 dev = pcidev_init(ata_via, PCI_ROM_ADDRESS); /* Actually no BAR setup needed at all. */
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000146 if (!dev)
147 return 1;
148
149 /* Test if a flash chip is attached. */
150 pci_write_long(dev, PCI_ROM_ADDRESS, (uint32_t)PCI_ROM_ADDRESS_MASK);
151 programmer_delay(90);
152 uint32_t base = pci_read_long(dev, PCI_ROM_ADDRESS);
153 msg_pdbg2("BROM base=0x%08x\n", base);
154 if ((base & PCI_ROM_ADDRESS_MASK) == 0) {
155 msg_pwarn("Controller thinks there is no ROM attached.\n");
156 }
157
158 if (!atavia_ready(dev)) {
159 msg_perr("Controller not ready.\n");
160 return 1;
161 }
162
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000163 register_par_master(&lpc_master_atavia, BUS_LPC, NULL);
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000164
165 return 0;
166}
167
168static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr)
169{
Stefan Tauner4f094752014-06-01 22:36:30 +0000170 msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000171 pci_write_long(dev, BROM_ADDR, (addr & ~3));
172 pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr));
173 pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr));
174
175 if (!atavia_ready(dev)) {
176 msg_perr("not ready after write\n");
177 }
178}
179
180static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr)
181{
182 pci_write_long(dev, BROM_ADDR, (addr & ~3));
183 pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr));
184
185 if (!atavia_ready(dev)) {
186 msg_perr("not ready after read\n");
187 }
188
189 uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff;
Stefan Tauner4f094752014-06-01 22:36:30 +0000190 msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
Jonathan Kollasch7f0f3fa2014-06-01 10:26:23 +0000191 return val;
192}