blob: 620e894607cfc9f9579c541e49fe9280cb6c0c50 [file] [log] [blame]
Uwe Hermannddd5c9e2010-02-21 21:17:00 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000015 */
16
Andrew Morgana0743832011-07-25 22:07:05 +000017#if defined(__i386__) || defined(__x86_64__)
18
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000019#include <stdlib.h>
20#include <string.h>
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000021#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000022#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000023#include "hwaccess.h"
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000024
25#define BIOS_ROM_ADDR 0x90
26#define BIOS_ROM_DATA 0x94
27
28#define REG_FLASH_ACCESS 0x58
29
30#define PCI_VENDOR_ID_HPT 0x1103
31
Stefan Tauner0ccec8f2014-06-01 23:49:03 +000032static uint32_t io_base_addr = 0;
33
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000034const struct dev_entry ata_hpt[] = {
Michael Karcher84486392010-02-24 00:04:40 +000035 {0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
36 {0x1103, 0x0005, NT, "Highpoint", "HPT372A/372N"},
37 {0x1103, 0x0006, NT, "Highpoint", "HPT302/302N"},
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000038
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000039 {0},
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000040};
41
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000042static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
43 chipaddr addr);
44static uint8_t atahpt_chip_readb(const struct flashctx *flash,
45 const chipaddr addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000046static const struct par_master par_master_atahpt = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000047 .chip_readb = atahpt_chip_readb,
48 .chip_readw = fallback_chip_readw,
49 .chip_readl = fallback_chip_readl,
50 .chip_readn = fallback_chip_readn,
51 .chip_writeb = atahpt_chip_writeb,
52 .chip_writew = fallback_chip_writew,
53 .chip_writel = fallback_chip_writel,
54 .chip_writen = fallback_chip_writen,
55};
56
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000057int atahpt_init(void)
58{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000059 struct pci_dev *dev = NULL;
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000060 uint32_t reg32;
61
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +000062 if (rget_io_perms())
63 return 1;
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000064
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000065 dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4);
66 if (!dev)
67 return 1;
68
69 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4);
Niklas Söderlund89edf362013-08-23 23:29:23 +000070 if (!io_base_addr)
71 return 1;
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000072
73 /* Enable flash access. */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000074 reg32 = pci_read_long(dev, REG_FLASH_ACCESS);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000075 reg32 |= (1 << 24);
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +000076 rpci_write_long(dev, REG_FLASH_ACCESS, reg32);
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000077
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +100078 register_par_master(&par_master_atahpt, BUS_PARALLEL, NULL);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000079
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000080 return 0;
81}
82
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000083static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
84 chipaddr addr)
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000085{
86 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
87 OUTB(val, io_base_addr + BIOS_ROM_DATA);
88}
89
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000090static uint8_t atahpt_chip_readb(const struct flashctx *flash,
91 const chipaddr addr)
Uwe Hermannddd5c9e2010-02-21 21:17:00 +000092{
93 OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
94 return INB(io_base_addr + BIOS_ROM_DATA);
95}
Andrew Morgana0743832011-07-25 22:07:05 +000096
97#else
98#error PCI port I/O access is not supported on this architecture yet.
99#endif