blob: 342a6e5ed19dd23c071a5c8fdf4694080e6c4bb9 [file] [log] [blame]
Donald Huang44ebb042011-02-22 17:16:34 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
6 * Copyright (C) 2008 coresystems GmbH
7 * Copyright (C) 2010 Google Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Donald Huang44ebb042011-02-22 17:16:34 +000017 */
18
19/*
20 * Contains the ITE IT85* SPI specific routines
21 */
22
23#if defined(__i386__) || defined(__x86_64__)
24
25#include <string.h>
David Hendricks4e748392011-02-28 23:58:15 +000026#include <stdio.h>
Donald Huang44ebb042011-02-22 17:16:34 +000027#include <stdlib.h>
28#include "flash.h"
Donald Huang44ebb042011-02-22 17:16:34 +000029#include "spi.h"
30#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000031#include "hwaccess.h"
Donald Huang44ebb042011-02-22 17:16:34 +000032
David Hendricks4e748392011-02-28 23:58:15 +000033#define MAX_TIMEOUT 100000
34#define MAX_TRY 5
35
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000036/* Constants for I/O ports */
Donald Huang44ebb042011-02-22 17:16:34 +000037#define ITE_SUPERIO_PORT1 0x2e
38#define ITE_SUPERIO_PORT2 0x4e
39
40/* Legacy I/O */
David Hendricks4e748392011-02-28 23:58:15 +000041#define LEGACY_KBC_PORT_DATA 0x60
42#define LEGACY_KBC_PORT_CMD 0x64
Donald Huang44ebb042011-02-22 17:16:34 +000043
44/* Constants for Logical Device registers */
45#define LDNSEL 0x07
Donald Huang44ebb042011-02-22 17:16:34 +000046
47/* These are standard Super I/O 16-bit base address registers */
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000048#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */
49#define SHM_IO_BAR1 0x61
Donald Huang44ebb042011-02-22 17:16:34 +000050
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000051/* The 8042 keyboard controller uses an input buffer and an output buffer to
52 * communicate with the host CPU. Both buffers are 1-byte depth. That means
Elyes HAOUAS124ef382018-03-27 12:15:09 +020053 * IBF is set to 1 when the host CPU sends a command to the input buffer
Carl-Daniel Hailfinger7f517a72011-03-08 00:23:49 +000054 * of the EC. IBF is cleared to 0 once the command is read by the EC.
55 */
Elyes HAOUASac01baa2018-05-28 16:52:21 +020056#define KB_IBF (1 << 1) /* Input Buffer Full */
57#define KB_OBF (1 << 0) /* Output Buffer Full */
David Hendricks4e748392011-02-28 23:58:15 +000058
Donald Huang44ebb042011-02-22 17:16:34 +000059/* IT8502 supports two access modes:
60 * LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode)
61 * LPC_IO: through I/O port (so called indirect memory)
62 */
63#undef LPC_MEMORY
64#define LPC_IO
65
66#ifdef LPC_IO
67/* macro to fill in indirect-access registers. */
68#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */
69#define INDIRECT_A1(base, value) OUTB(value, (base) + 1)
70#define INDIRECT_A2(base, value) OUTB(value, (base) + 2)
71#define INDIRECT_A3(base, value) OUTB(value, (base) + 3)
72#define INDIRECT_READ(base) INB((base) + 4)
73#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4)
74#endif /* LPC_IO */
75
76#ifdef LPC_IO
Jacob Garberafc3ad62019-06-24 16:05:28 -060077static unsigned int shm_io_base;
Donald Huang44ebb042011-02-22 17:16:34 +000078#endif
Jacob Garberafc3ad62019-06-24 16:05:28 -060079static unsigned char *ce_high, *ce_low;
Donald Huang44ebb042011-02-22 17:16:34 +000080static int it85xx_scratch_rom_reenter = 0;
81
David Hendricks4e748392011-02-28 23:58:15 +000082/* This function will poll the keyboard status register until either
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +000083 * an expected value shows up, or the timeout is reached.
84 * timeout is in usec.
David Hendricks4e748392011-02-28 23:58:15 +000085 *
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +000086 * Returns: 0 -- the expected value showed up.
87 * 1 -- timeout.
David Hendricks4e748392011-02-28 23:58:15 +000088 */
Uwe Hermann91f4afa2011-07-28 08:13:25 +000089static int wait_for(const unsigned int mask, const unsigned int expected_value,
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +000090 const int timeout, const char * error_message,
91 const char * function_name, const int lineno)
Uwe Hermann91f4afa2011-07-28 08:13:25 +000092{
David Hendricks4e748392011-02-28 23:58:15 +000093 int time_passed;
94
95 for (time_passed = 0;; ++time_passed) {
96 if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value)
97 return 0;
98 if (time_passed >= timeout)
99 break;
100 programmer_delay(1);
101 }
102 if (error_message)
103 msg_perr("%s():%d %s", function_name, lineno, error_message);
104 return 1;
105}
106
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000107/* IT8502 employs a scratch RAM when flash is being updated. Call the following
David Hendricks4e748392011-02-28 23:58:15 +0000108 * two functions before/after flash erase/program. */
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600109static void it85xx_enter_scratch_rom(void)
Donald Huang44ebb042011-02-22 17:16:34 +0000110{
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000111 int ret, tries;
David Hendricks4e748392011-02-28 23:58:15 +0000112
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000113 msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000114 if (it85xx_scratch_rom_reenter > 0)
115 return;
David Hendricks4e748392011-02-28 23:58:15 +0000116
117#if 0
118 /* FIXME: this a workaround for the bug that SMBus signal would
119 * interfere the EC firmware update. Should be removed if
120 * we find out the root cause. */
121 ret = system("stop powerd >&2");
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000122 if (ret)
David Hendricks4e748392011-02-28 23:58:15 +0000123 msg_perr("Cannot stop powerd.\n");
David Hendricks4e748392011-02-28 23:58:15 +0000124#endif
125
126 for (tries = 0; tries < MAX_TRY; ++tries) {
127 /* Wait until IBF (input buffer) is not full. */
128 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
129 "* timeout at waiting for IBF==0.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000130 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000131 continue;
132
133 /* Copy EC firmware to SRAM. */
134 OUTB(0xb4, LEGACY_KBC_PORT_CMD);
135
136 /* Confirm EC has taken away the command. */
137 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
138 "* timeout at taking command.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000139 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000140 continue;
141
142 /* Waiting for OBF (output buffer) has data.
143 * Note sometimes the replied command might be stolen by kernel
144 * ISR so that it is okay as long as the command is 0xFA. */
145 if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0))
146 msg_pdbg("%s():%d * timeout at waiting for OBF.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000147 __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000148 if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) {
149 break;
150 } else {
151 msg_perr("%s():%d * not run on SRAM ret=%d\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000152 __func__, __LINE__, ret);
David Hendricks4e748392011-02-28 23:58:15 +0000153 continue;
154 }
155 }
156
157 if (tries < MAX_TRY) {
158 /* EC already runs on SRAM */
159 it85xx_scratch_rom_reenter++;
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000160 msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000161 } else {
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000162 msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000163 }
Donald Huang44ebb042011-02-22 17:16:34 +0000164}
165
Jacob Garberbeeb8bc2019-06-21 15:24:17 -0600166static void it85xx_exit_scratch_rom(void)
Donald Huang44ebb042011-02-22 17:16:34 +0000167{
David Hendricks4e748392011-02-28 23:58:15 +0000168#if 0
169 int ret;
170#endif
171 int tries;
172
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000173 msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000174 if (it85xx_scratch_rom_reenter <= 0)
175 return;
David Hendricks4e748392011-02-28 23:58:15 +0000176
177 for (tries = 0; tries < MAX_TRY; ++tries) {
178 /* Wait until IBF (input buffer) is not full. */
179 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
180 "* timeout at waiting for IBF==0.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000181 __func__, __LINE__))
David Hendricks4e748392011-02-28 23:58:15 +0000182 continue;
183
184 /* Exit SRAM. Run on flash. */
185 OUTB(0xFE, LEGACY_KBC_PORT_CMD);
186
187 /* Confirm EC has taken away the command. */
188 if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
189 "* timeout at taking command.\n",
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000190 __func__, __LINE__)) {
David Hendricks4e748392011-02-28 23:58:15 +0000191 /* We cannot ensure if EC has exited update mode.
192 * If EC is in normal mode already, a further 0xFE
193 * command will reboot system. So, exit loop here. */
194 tries = MAX_TRY;
195 break;
196 }
197
198 break;
199 }
200
201 if (tries < MAX_TRY) {
202 it85xx_scratch_rom_reenter = 0;
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000203 msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000204 } else {
Uwe Hermanne187d5e2011-07-29 20:13:45 +0000205 msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
David Hendricks4e748392011-02-28 23:58:15 +0000206 }
207
208#if 0
209 /* FIXME: this a workaround for the bug that SMBus signal would
210 * interfere the EC firmware update. Should be removed if
211 * we find out the root cause. */
212 ret = system("start powerd >&2");
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000213 if (ret)
David Hendricks4e748392011-02-28 23:58:15 +0000214 msg_perr("Cannot start powerd again.\n");
David Hendricks4e748392011-02-28 23:58:15 +0000215#endif
Donald Huang44ebb042011-02-22 17:16:34 +0000216}
217
David Hendricks8bb20212011-06-14 01:35:36 +0000218static int it85xx_shutdown(void *data)
219{
220 msg_pdbg("%s():%d\n", __func__, __LINE__);
221 it85xx_exit_scratch_rom();
222
223 return 0; /* FIXME: Should probably return something meaningful */
224}
225
Anastasia Klimchuk5783c042020-11-17 16:09:51 +1100226/* According to ITE 8502 document, the procedure to follow mode is following:
227 * 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
228 * 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
229 * with data)
230 * 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
231 * data from MISO)
232 */
233static int it85xx_spi_send_command(const struct flashctx *flash,
234 unsigned int writecnt, unsigned int readcnt,
235 const unsigned char *writearr,
236 unsigned char *readarr)
237{
238 unsigned int i;
239
240 it85xx_enter_scratch_rom();
241 /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the
242 * temporary flash state may halt the EC.
243 */
244
245#ifdef LPC_IO
246 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
247 INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
248 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff);
249#endif
250#ifdef LPC_MEMORY
251 mmio_writeb(0, ce_high);
252#endif
253 for (i = 0; i < writecnt; ++i) {
254#ifdef LPC_IO
255 INDIRECT_WRITE(shm_io_base, writearr[i]);
256#endif
257#ifdef LPC_MEMORY
258 mmio_writeb(writearr[i], ce_low);
259#endif
260 }
261 for (i = 0; i < readcnt; ++i) {
262#ifdef LPC_IO
263 readarr[i] = INDIRECT_READ(shm_io_base);
264#endif
265#ifdef LPC_MEMORY
266 readarr[i] = mmio_readb(ce_low);
267#endif
268 }
269#ifdef LPC_IO
270 INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
271 INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
272#endif
273#ifdef LPC_MEMORY
274 mmio_writeb(0, ce_high);
275#endif
276
277 return 0;
278}
279
280static const struct spi_master spi_master_it85xx = {
281 .max_data_read = 64,
282 .max_data_write = 64,
283 .command = it85xx_spi_send_command,
284 .multicommand = default_spi_send_multicommand,
285 .read = default_spi_read,
286 .write_256 = default_spi_write_256,
287 .write_aai = default_spi_write_aai,
288};
289
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000290static int it85xx_spi_common_init(struct superio s)
Donald Huang44ebb042011-02-22 17:16:34 +0000291{
292 chipaddr base;
293
294 msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000295 s.vendor);
Donald Huang44ebb042011-02-22 17:16:34 +0000296
David Hendricks8bb20212011-06-14 01:35:36 +0000297 if (register_shutdown(it85xx_shutdown, NULL))
298 return 1;
299
Donald Huang44ebb042011-02-22 17:16:34 +0000300#ifdef LPC_IO
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000301 /* Get LPCPNP of SHM. That's big-endian. */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000302 sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
303 shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
304 sio_read(s.port, SHM_IO_BAR1);
Donald Huang44ebb042011-02-22 17:16:34 +0000305 msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
306 shm_io_base);
307
308 /* These pointers are not used directly. They will be send to EC's
309 * register for indirect access. */
310 base = 0xFFFFF000;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000311 ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
312 ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
Donald Huang44ebb042011-02-22 17:16:34 +0000313
314 /* pre-set indirect-access registers since in most of cases they are
315 * 0xFFFFxx00. */
316 INDIRECT_A0(shm_io_base, base & 0xFF);
317 INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
318 INDIRECT_A3(shm_io_base, (base >> 24));
319#endif
320#ifdef LPC_MEMORY
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000321 /* FIXME: We should block accessing that region for anything else.
322 * Major TODO here, and it will be a lot of work.
323 */
324 base = (chipaddr)physmap("it85 communication", 0xFFFFF000, 0x1000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000325 if (base == (chipaddr)ERROR_PTR)
326 return 1;
327
Donald Huang44ebb042011-02-22 17:16:34 +0000328 msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
329 (unsigned int)base);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000330 ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
331 ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
Donald Huang44ebb042011-02-22 17:16:34 +0000332#endif
333
Donald Huang44ebb042011-02-22 17:16:34 +0000334 return 0;
335}
336
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000337int it85xx_spi_init(struct superio s)
Donald Huang44ebb042011-02-22 17:16:34 +0000338{
339 int ret;
340
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000341 if (!(internal_buses_supported & BUS_FWH)) {
Donald Huang44ebb042011-02-22 17:16:34 +0000342 msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
343 return 1;
344 }
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000345 ret = it85xx_spi_common_init(s);
Donald Huang44ebb042011-02-22 17:16:34 +0000346 msg_pdbg("FWH: %s():%d ret=%d\n", __func__, __LINE__, ret);
347 if (!ret) {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000348 msg_pdbg("%s: internal_buses_supported=0x%x\n", __func__,
349 internal_buses_supported);
350 /* Check for FWH because IT85 listens to FWH cycles.
351 * FIXME: The big question is whether FWH cycles are necessary
352 * for communication even if LPC_IO is defined.
353 */
354 if (internal_buses_supported & BUS_FWH)
355 msg_pdbg("Registering IT85 SPI.\n");
356 /* FIXME: Really leave FWH enabled? We can't use this region
357 * anymore since accessing it would mess up IT85 communication.
358 * If we decide to disable FWH for this region, we should print
359 * a debug message about it.
360 */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000361 /* Set this as SPI controller. */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000362 register_spi_master(&spi_master_it85xx);
Donald Huang44ebb042011-02-22 17:16:34 +0000363 }
364 return ret;
365}
366
Donald Huang44ebb042011-02-22 17:16:34 +0000367#endif