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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000024 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000029#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000033#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000034#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000035
Nico Huberd54e4f42017-03-23 23:45:47 +010036/* Sunrise Point */
37
38/* Added HSFS Status bits */
39#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
40#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
41#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
42#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
43/* HSFS_BERASE vanished */
44
45/*
46 * HSFC and HSFS 16-bit registers are combined into the 32-bit
47 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
48 * however we still treat them separately in order to reuse code.
49 */
50
51/* Changed HSFC Control bits */
52#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
53#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
54/* New HSFC Control bit */
55#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
56#define HSFC_WET (0x1 << HSFC_WET_OFF)
57
58#define PCH100_FADDR_FLA 0x07ffffff
59
60#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
61#define DLOCK_BMWAG_LOCKDN_OFF 0
62#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
63#define DLOCK_BMRAG_LOCKDN_OFF 1
64#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
65#define DLOCK_SBMWAG_LOCKDN_OFF 2
66#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
67#define DLOCK_SBMRAG_LOCKDN_OFF 3
68#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
69#define DLOCK_PR0_LOCKDN_OFF 8
70#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
71#define DLOCK_PR1_LOCKDN_OFF 9
72#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
73#define DLOCK_PR2_LOCKDN_OFF 10
74#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
75#define DLOCK_PR3_LOCKDN_OFF 11
76#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
77#define DLOCK_PR4_LOCKDN_OFF 12
78#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
79#define DLOCK_SSEQ_LOCKDN_OFF 16
80#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
81
82#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
83#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
84
85#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
86#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
87#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
88#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
89
Stefan Reinauera9424d52008-06-27 16:28:34 +000090/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000091#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
92#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
93#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
94#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
95#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
96#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
97#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
98#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
99#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
100#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
101#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
102 /* 6-12: reserved */
103#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
104#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
105#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
106#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
107#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
108#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
109
110#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
111#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
112#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
113#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
114#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
115 /* 3-7: reserved */
116#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
117#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
118 /* 14: reserved */
119#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
120#define HSFC_SME (0x1 << HSFC_SME_OFF)
121
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000122#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100123#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000124#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000125
Stefan Tauner29c80832011-06-12 08:14:10 +0000126#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
127#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
128
129#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000130#define PR_WP_OFF 31 /* 31: write protection enable */
131#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000132
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000133#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000134#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
135#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
136#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
137#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
138#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
139#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
140#define SSFS_AEL_OFF 4 /* Access Error Log */
141#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000142/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000143#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000144
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000146/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000147 * therefore SSFC bits are off by 8. */
148 /* 0: reserved */
149#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
150#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
151#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
152#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
153#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
154#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
155#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
156#define SSFC_COP (0x7 << SSFC_COP_OFF)
157 /* 7: reserved */
158#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
159#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
160#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
161#define SSFC_DS (0x1 << SSFC_DS_OFF)
162#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
163#define SSFC_SME (0x1 << SSFC_SME_OFF)
164#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
165#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
166#define SSFC_SCF_20MHZ 0x00000000
167#define SSFC_SCF_33MHZ 0x01000000
168 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000169#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000170
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000171#define ICH9_REG_PREOP 0x94 /* 16 Bits */
172#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
173#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000174
Stefan Tauner29c80832011-06-12 08:14:10 +0000175#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
176#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
177
Stefan Tauner1e146392011-09-15 23:52:55 +0000178#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
179#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
180#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
181/* The individual fields of the VSCC registers are defined in the file
182 * ich_descriptors.h. The reason is that the same layout is also used in the
183 * flash descriptor to define the properties of the different flash chips
184 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
185 * with the information from the descriptor on startup depending on the actual
186 * chip(s) detected. */
187
Stefan Taunerbd649e42011-07-01 00:39:16 +0000188#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
189#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
190#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
191
Dominik Geyerb46acba2008-05-16 12:55:55 +0000192// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000193#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
194#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
195#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
196#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000197
Stefan Reinauera9424d52008-06-27 16:28:34 +0000198// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000199#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000200#define SPIS_SCIP 0x0001
201#define SPIS_GRANT 0x0002
202#define SPIS_CDS 0x0004
203#define SPIS_FCERR 0x0008
204#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000205
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000206/* VIA SPI is compatible with ICH7, but maxdata
207 to transfer is 16 bytes.
208
209 DATA byte count on ICH7 is 8:13, on VIA 8:11
210
211 bit 12 is port select CS0 CS1
212 bit 13 is FAST READ enable
213 bit 7 is used with fast read and one shot controls CS de-assert?
214*/
215
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000216#define ICH7_REG_SPIC 0x02 /* 16 Bits */
217#define SPIC_SCGO 0x0002
218#define SPIC_ACS 0x0004
219#define SPIC_SPOP 0x0008
220#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000221
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000222#define ICH7_REG_SPIA 0x04 /* 32 Bits */
223#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
224#define ICH7_REG_PREOP 0x54 /* 16 Bits */
225#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
226#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000227
FENG yu ningc05a2952008-12-08 18:16:58 +0000228/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000229static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000230
Stefan Taunera8d838d2011-11-06 23:51:09 +0000231static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000232uint32_t ichspi_bbar = 0;
233
Michael Karchera4448d92010-07-22 18:04:15 +0000234static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000235
Dominik Geyerb46acba2008-05-16 12:55:55 +0000236typedef struct _OPCODE {
237 uint8_t opcode; //This commands spi opcode
238 uint8_t spi_type; //This commands spi type
239 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
240} OPCODE;
241
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000242/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000243 * Preop 1: Write Enable
244 * Preop 2: Write Status register enable
245 *
246 * OP 0: Write address
247 * OP 1: Read Address
248 * OP 2: ERASE block
249 * OP 3: Read Status register
250 * OP 4: Read ID
251 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000252 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000253 * OP 7: Chip erase
254 */
255typedef struct _OPCODES {
256 uint8_t preop[2];
257 OPCODE opcode[8];
258} OPCODES;
259
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000260static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000261
262/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000263static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000264{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000265 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000266}
267
Uwe Hermann09e04f72009-05-16 22:36:00 +0000268static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000269{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000270 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000271}
272
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000273static uint16_t REGREAD8(int X)
274{
275 return mmio_readb(ich_spibar + X);
276}
277
Stefan Taunerccd92a12011-07-01 00:39:01 +0000278#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
279#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
280#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000281
Dominik Geyerb46acba2008-05-16 12:55:55 +0000282/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000283static int find_opcode(OPCODES *op, uint8_t opcode);
284static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000285static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000286static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000287static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000288 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000289
FENG yu ningf041e9b2008-12-15 02:32:11 +0000290/* for pairing opcodes with their required preop */
291struct preop_opcode_pair {
292 uint8_t preop;
293 uint8_t opcode;
294};
295
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000296/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000297const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000298 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
299 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
300 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
301 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
302 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
303 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000304 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
305 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000306 {JEDEC_EWSR, JEDEC_WRSR},
307 {0,}
308};
309
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000310/* Reasonable default configuration. Needs ad-hoc modifications if we
311 * encounter unlisted opcodes. Fun.
312 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000313static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000314 {
315 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000316 JEDEC_EWSR,
317 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000318 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000319 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000320 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000321 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000322 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000323 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000324 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000325 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000326 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
327 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000328};
329
Helge Wagner738e2522010-10-05 22:06:05 +0000330/* List of opcodes with their corresponding spi_type
331 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
332 * is needed which is currently not in the chipset OPCODE table
333 */
334static OPCODE POSSIBLE_OPCODES[] = {
335 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
336 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
337 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
338 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
339 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
340 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
341 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
342 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
343 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
344 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
345 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
346};
347
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000348static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000349
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000350/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000351static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000352{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000353 OPCODE oc;
354 const char *t;
355 const char *a;
356 uint8_t i;
357 static const char *const spi_type[4] = {
358 "read w/o addr",
359 "write w/o addr",
360 "read w/ addr",
361 "write w/ addr"
362 };
363 static const char *const atomic_type[3] = {
364 "none",
365 " 0 ",
366 " 1 "
367 };
368
369 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000370 return;
371
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000372 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000373 for (i = 0; i < 8; i++) {
374 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000375 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
376 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
377 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000378 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000379 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
380 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000381}
382
Nico Huberd54e4f42017-03-23 23:45:47 +0100383#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
384#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000385
Stefan Tauner55206942011-06-11 09:53:22 +0000386static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
387{
388 msg_pdbg("HSFS: ");
389 pprint_reg(HSFS, FDONE, reg_val, ", ");
390 pprint_reg(HSFS, FCERR, reg_val, ", ");
391 pprint_reg(HSFS, AEL, reg_val, ", ");
Nico Huberd54e4f42017-03-23 23:45:47 +0100392 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) {
393 pprint_reg(HSFS, BERASE, reg_val, ", ");
394 }
Stefan Tauner55206942011-06-11 09:53:22 +0000395 pprint_reg(HSFS, SCIP, reg_val, ", ");
Nico Huberd54e4f42017-03-23 23:45:47 +0100396 if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
397 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
398 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
399 }
Stefan Tauner55206942011-06-11 09:53:22 +0000400 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
401 pprint_reg(HSFS, FDV, reg_val, ", ");
402 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
403}
404
405static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
406{
407 msg_pdbg("HSFC: ");
408 pprint_reg(HSFC, FGO, reg_val, ", ");
Nico Huberd54e4f42017-03-23 23:45:47 +0100409 if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) {
410 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
411 } else {
412 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
413 pprint_reg(HSFC, WET, reg_val, ", ");
414 }
Stefan Tauner55206942011-06-11 09:53:22 +0000415 pprint_reg(HSFC, FDBC, reg_val, ", ");
416 pprint_reg(HSFC, SME, reg_val, "\n");
417}
418
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000419static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
420{
421 msg_pdbg("SSFS: ");
422 pprint_reg(SSFS, SCIP, reg_val, ", ");
423 pprint_reg(SSFS, FDONE, reg_val, ", ");
424 pprint_reg(SSFS, FCERR, reg_val, ", ");
425 pprint_reg(SSFS, AEL, reg_val, "\n");
426}
427
428static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
429{
430 msg_pdbg("SSFC: ");
431 pprint_reg(SSFC, SCGO, reg_val, ", ");
432 pprint_reg(SSFC, ACS, reg_val, ", ");
433 pprint_reg(SSFC, SPOP, reg_val, ", ");
434 pprint_reg(SSFC, COP, reg_val, ", ");
435 pprint_reg(SSFC, DBC, reg_val, ", ");
436 pprint_reg(SSFC, SME, reg_val, ", ");
437 pprint_reg(SSFC, SCF, reg_val, "\n");
438}
439
Nico Huberd54e4f42017-03-23 23:45:47 +0100440static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
441{
442 msg_pdbg("DLOCK: ");
443 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
444 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
445 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
446 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
447 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
448 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
449 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
450 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
451 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
452 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
453}
454
455static struct {
456 size_t reg_ssfsc;
457 size_t reg_preop;
458 size_t reg_optype;
459 size_t reg_opmenu;
460} swseq_data;
461
Helge Wagner738e2522010-10-05 22:06:05 +0000462static uint8_t lookup_spi_type(uint8_t opcode)
463{
464 int a;
465
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000466 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000467 if (POSSIBLE_OPCODES[a].opcode == opcode)
468 return POSSIBLE_OPCODES[a].spi_type;
469 }
470
471 return 0xFF;
472}
473
474static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
475{
476 uint8_t spi_type;
477
478 spi_type = lookup_spi_type(opcode);
479 if (spi_type > 3) {
480 /* Try to guess spi type from read/write sizes.
481 * The following valid writecnt/readcnt combinations exist:
482 * writecnt = 4, readcnt >= 0
483 * writecnt = 1, readcnt >= 0
484 * writecnt >= 4, readcnt = 0
485 * writecnt >= 1, readcnt = 0
486 * writecnt >= 1 is guaranteed for all commands.
487 */
488 if (readcnt == 0)
489 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
490 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
491 * bytes are actual the address, they go to the bus anyhow
492 */
493 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
494 else if (writecnt == 1) // and readcnt is > 0
495 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
496 else if (writecnt == 4) // and readcnt is > 0
497 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000498 else // we have an invalid case
499 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000500 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000501 int oppos = 2; // use original JEDEC_BE_D8 offset
502 curopcodes->opcode[oppos].opcode = opcode;
503 curopcodes->opcode[oppos].spi_type = spi_type;
504 program_opcodes(curopcodes, 0);
505 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000506 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000507 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000508}
509
Uwe Hermann09e04f72009-05-16 22:36:00 +0000510static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000511{
512 int a;
513
Stefan Tauner50e7c602011-11-08 10:55:54 +0000514 if (op == NULL) {
515 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
516 return -1;
517 }
518
FENG yu ningc05a2952008-12-08 18:16:58 +0000519 for (a = 0; a < 8; a++) {
520 if (op->opcode[a].opcode == opcode)
521 return a;
522 }
523
524 return -1;
525}
526
Uwe Hermann09e04f72009-05-16 22:36:00 +0000527static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000528{
529 int a;
530
Stefan Tauner50e7c602011-11-08 10:55:54 +0000531 if (op == NULL) {
532 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
533 return -1;
534 }
535
FENG yu ningc05a2952008-12-08 18:16:58 +0000536 for (a = 0; a < 2; a++) {
537 if (op->preop[a] == preop)
538 return a;
539 }
540
541 return -1;
542}
543
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000544/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000545static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000546{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000547 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000548 uint16_t preop, optype;
549 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000550
551 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000552 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000553 return -1;
554 }
555
Stefan Taunera8d838d2011-11-06 23:51:09 +0000556 switch (ich_generation) {
557 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000558 case CHIPSET_TUNNEL_CREEK:
559 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000560 preop = REGREAD16(ICH7_REG_PREOP);
561 optype = REGREAD16(ICH7_REG_OPTYPE);
562 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
563 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
564 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000565 case CHIPSET_ICH8:
566 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100567 preop = REGREAD16(swseq_data.reg_preop);
568 optype = REGREAD16(swseq_data.reg_optype);
569 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
570 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000571 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000572 }
573
574 op->preop[0] = (uint8_t) preop;
575 op->preop[1] = (uint8_t) (preop >> 8);
576
577 for (a = 0; a < 8; a++) {
578 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
579 optype >>= 2;
580 }
581
582 for (a = 0; a < 4; a++) {
583 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
584 opmenu[0] >>= 8;
585 }
586
587 for (a = 4; a < 8; a++) {
588 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
589 opmenu[1] >>= 8;
590 }
591
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000592 /* No preopcodes used by default. */
593 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000594 op->opcode[a].atomic = 0;
595
FENG yu ningc05a2952008-12-08 18:16:58 +0000596 return 0;
597}
598
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000599static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000600{
601 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000602 uint16_t preop, optype;
603 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000604
605 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000606 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000607 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000608 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000609 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000610
Stefan Reinauera9424d52008-06-27 16:28:34 +0000611 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000612 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000613 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000614 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000615 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000616
Stefan Reinauera9424d52008-06-27 16:28:34 +0000617 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000618 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000619 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000620 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000621 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000622
Stefan Tauner92d6a862013-10-25 00:33:37 +0000623 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000624 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000625 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000626 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000627 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000628
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000629 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000630 switch (ich_generation) {
631 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000632 case CHIPSET_TUNNEL_CREEK:
633 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000634 /* Register undo only for enable_undo=1, i.e. first call. */
635 if (enable_undo) {
636 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
637 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
638 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
639 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
640 }
641 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
642 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
643 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
644 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000645 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000646 case CHIPSET_ICH8:
647 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000648 /* Register undo only for enable_undo=1, i.e. first call. */
649 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100650 rmmio_valw(ich_spibar + swseq_data.reg_preop);
651 rmmio_valw(ich_spibar + swseq_data.reg_optype);
652 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
653 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000654 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100655 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
656 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
657 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
658 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000659 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000660 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000661
662 return 0;
663}
664
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000665/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000666 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
667 * FIXME: this should also check for
668 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
669 * - at least one erasing opcode (lots.)
670 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
671 * - necessary preops? (EWSR, WREN, ...?)
672 */
673static int ich_missing_opcodes()
674{
675 uint8_t ops[] = {
676 JEDEC_READ,
677 JEDEC_RDSR,
678 0
679 };
680 int i = 0;
681 while (ops[i] != 0) {
682 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
683 if (find_opcode(curopcodes, ops[i]) == -1)
684 return -1;
685 i++;
686 }
687 return 0;
688}
689
690/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000691 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
692 * it didn't stick.
693 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000694static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000695{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000696 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000697 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000698 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000699 case CHIPSET_TUNNEL_CREEK:
700 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000701 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000702 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000703 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000704 case CHIPSET_BAYTRAIL:
705 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000706 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000707 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000708 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000709 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000710 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000711 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000712
713 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
714 if (ichspi_bbar) {
715 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
716 ichspi_bbar);
717 }
718 min_addr &= BBAR_MASK;
719 ichspi_bbar |= min_addr;
720 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
721 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
722
723 /* We don't have any option except complaining. And if the write
724 * failed, the restore will fail as well, so no problem there.
725 */
726 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000727 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
728 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000729}
730
Stefan Tauner8b391b82011-08-09 01:49:34 +0000731/* Read len bytes from the fdata/spid register into the data array.
732 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000733 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000734 * may even crash.
735 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000736static void ich_read_data(uint8_t *data, int len, int reg0_off)
Stefan Tauner8b391b82011-08-09 01:49:34 +0000737 {
738 int i;
739 uint32_t temp32 = 0;
740
741 for (i = 0; i < len; i++) {
742 if ((i % 4) == 0)
743 temp32 = REGREAD32(reg0_off + i);
744
745 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
746 }
747}
748
749/* Fill len bytes from the data array into the fdata/spid registers.
750 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000751 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000752 * following the data registers.
753 */
754static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
755{
756 uint32_t temp32 = 0;
757 int i;
758
759 if (len <= 0)
760 return;
761
762 for (i = 0; i < len; i++) {
763 if ((i % 4) == 0)
764 temp32 = 0;
765
766 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
767
768 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
769 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
770 }
771 i--;
772 if ((i % 4) != 3) /* Write remaining data to regs. */
773 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
774}
775
FENG yu ningf041e9b2008-12-15 02:32:11 +0000776/* This function generates OPCODES from or programs OPCODES to ICH according to
777 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000778 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000779 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000780 */
Michael Karchera4448d92010-07-22 18:04:15 +0000781static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000782{
783 int rc = 0;
784 OPCODES *curopcodes_done;
785
786 if (curopcodes)
787 return 0;
788
789 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000790 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000791 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000792 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000793 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000794 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000795 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000796 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000797 }
798
799 if (rc) {
800 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000801 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000802 return 1;
803 } else {
804 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000805 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000806 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000807 return 0;
808 }
809}
810
Stefan Reinauer43119562008-11-02 19:51:50 +0000811static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000812 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000813{
814 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000815 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000816 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000817 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000818 uint64_t opmenu;
819 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000820
821 /* Is it a write command? */
822 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
823 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
824 write_cmd = 1;
825 }
826
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000827 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
828 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
829 programmer_delay(10);
830 }
831 if (!timeout) {
832 msg_perr("Error: SCIP never cleared!\n");
833 return 1;
834 }
835
Stefan Tauner10b3e222011-07-01 00:39:23 +0000836 /* Program offset in flash into SPIA while preserving reserved bits. */
837 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
838 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000839
Stefan Tauner10b3e222011-07-01 00:39:23 +0000840 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000841 if (write_cmd && (datalength != 0))
842 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000843
844 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000845 temp16 = REGREAD16(ICH7_REG_SPIS);
846 /* keep reserved bits */
847 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000848 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000849 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000850 REGWRITE16(ICH7_REG_SPIS, temp16);
851
852 /* Assemble SPIC */
853 temp16 = 0;
854
855 if (datalength != 0) {
856 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000857 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000858 }
859
860 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000861 opmenu = REGREAD32(ICH7_REG_OPMENU);
862 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
863
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000864 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
865 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000866 break;
867 }
868 opmenu >>= 8;
869 }
870 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000871 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000872 return 1;
873 }
874 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000875
Michael Karcher136125a2011-04-29 22:11:36 +0000876 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
877 /* Handle Atomic. Atomic commands include three steps:
878 - sending the preop (mainly EWSR or WREN)
879 - sending the main command
880 - waiting for the busy bit (WIP) to be cleared
881 This means the timeout must be sufficient for chip erase
882 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000883 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000884 switch (op.atomic) {
885 case 2:
886 /* Select second preop. */
887 temp16 |= SPIC_SPOP;
888 /* And fall through. */
889 case 1:
890 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000891 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000892 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000893 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000894 }
895
896 /* Start */
897 temp16 |= SPIC_SCGO;
898
899 /* write it */
900 REGWRITE16(ICH7_REG_SPIC, temp16);
901
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000902 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000903 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
904 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000905 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000906 }
907 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000908 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
909 REGREAD16(ICH7_REG_SPIS));
910 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000911 }
912
Sean Nelson316a29f2010-05-07 20:09:04 +0000913 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000914 temp16 = REGREAD16(ICH7_REG_SPIS);
915 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000916 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000917 /* keep reserved bits */
918 temp16 &= SPIS_RESERVED_MASK;
919 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000920 return 1;
921 }
922
Stefan Tauner8b391b82011-08-09 01:49:34 +0000923 if ((!write_cmd) && (datalength != 0))
924 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000925
926 return 0;
927}
928
Stefan Reinauer43119562008-11-02 19:51:50 +0000929static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000930 uint8_t datalength, uint8_t * data)
931{
932 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000933 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000934 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000935 uint64_t opmenu;
936 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000937
938 /* Is it a write command? */
939 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
940 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
941 write_cmd = 1;
942 }
943
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000944 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100945 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000946 programmer_delay(10);
947 }
948 if (!timeout) {
949 msg_perr("Error: SCIP never cleared!\n");
950 return 1;
951 }
952
Stefan Tauner10b3e222011-07-01 00:39:23 +0000953 /* Program offset in flash into FADDR while preserve the reserved bits
954 * and clearing the 25. address bit which is only useable in hwseq. */
955 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
956 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000957
958 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000959 if (write_cmd && (datalength != 0))
960 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000961
962 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100963 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000964 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000965 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000966 /* Clear cycle done and cycle error status registers */
967 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100968 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000969
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000970 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000971 temp32 |= SSFC_SCF_20MHZ;
972
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000973 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000974 if (datalength != 0) {
975 uint32_t datatemp;
976 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000977 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
978 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000979 temp32 |= datatemp;
980 }
981
982 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000983 opmenu = REGREAD32(ICH9_REG_OPMENU);
984 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
985
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000986 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
987 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000988 break;
989 }
990 opmenu >>= 8;
991 }
992 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000993 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000994 return 1;
995 }
996 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000997
Michael Karcher136125a2011-04-29 22:11:36 +0000998 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
999 /* Handle Atomic. Atomic commands include three steps:
1000 - sending the preop (mainly EWSR or WREN)
1001 - sending the main command
1002 - waiting for the busy bit (WIP) to be cleared
1003 This means the timeout must be sufficient for chip erase
1004 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001005 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001006 switch (op.atomic) {
1007 case 2:
1008 /* Select second preop. */
1009 temp32 |= SSFC_SPOP;
1010 /* And fall through. */
1011 case 1:
1012 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001013 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001014 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001015 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001016 }
1017
1018 /* Start */
1019 temp32 |= SSFC_SCGO;
1020
1021 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001022 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001023
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001024 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001025 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001026 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001027 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001028 }
1029 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001030 msg_perr("timeout, REG_SSFS=0x%08x\n",
1031 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001032 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001033 }
1034
Sean Nelson316a29f2010-05-07 20:09:04 +00001035 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001036 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001037 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001038 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001039 prettyprint_ich9_reg_ssfs(temp32);
1040 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001041 /* keep reserved bits */
1042 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1043 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001044 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001045 return 1;
1046 }
1047
Stefan Tauner8b391b82011-08-09 01:49:34 +00001048 if ((!write_cmd) && (datalength != 0))
1049 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001050
1051 return 0;
1052}
1053
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001054static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001055 uint8_t datalength, uint8_t * data)
1056{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001057 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001058 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001059
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001060 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001061 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001062 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001063 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001064
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001065 if (datalength > maxlength) {
1066 msg_perr("%s: Internal command size error for "
1067 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1068 __func__, op.opcode, datalength, maxlength);
1069 return SPI_INVALID_LENGTH;
1070 }
1071
Stefan Taunera8d838d2011-11-06 23:51:09 +00001072 switch (ich_generation) {
1073 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001074 case CHIPSET_TUNNEL_CREEK:
1075 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001076 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001077 case CHIPSET_ICH8:
1078 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001079 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001080 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001081}
1082
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001083static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
1084 unsigned int readcnt,
1085 const unsigned char *writearr,
1086 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001087{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001088 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001089 int opcode_index = -1;
1090 const unsigned char cmd = *writearr;
1091 OPCODE *opcode;
1092 uint32_t addr = 0;
1093 uint8_t *data;
1094 int count;
1095
Dominik Geyerb46acba2008-05-16 12:55:55 +00001096 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001097 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001098 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001099 if (!ichspi_lock)
1100 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001101 if (opcode_index == SPI_INVALID_LENGTH) {
1102 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1103 return SPI_INVALID_LENGTH;
1104 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001105 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1106 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001107 return SPI_INVALID_OPCODE;
1108 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001109 }
1110
1111 opcode = &(curopcodes->opcode[opcode_index]);
1112
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001113 /* The following valid writecnt/readcnt combinations exist:
1114 * writecnt = 4, readcnt >= 0
1115 * writecnt = 1, readcnt >= 0
1116 * writecnt >= 4, readcnt = 0
1117 * writecnt >= 1, readcnt = 0
1118 * writecnt >= 1 is guaranteed for all commands.
1119 */
1120 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1121 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001122 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001123 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1124 writecnt);
1125 return SPI_INVALID_LENGTH;
1126 }
1127 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1128 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001129 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001130 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1131 writecnt);
1132 return SPI_INVALID_LENGTH;
1133 }
1134 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1135 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001136 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001137 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1138 writecnt);
1139 return SPI_INVALID_LENGTH;
1140 }
1141 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1142 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1143 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001144 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001145 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1146 readcnt);
1147 return SPI_INVALID_LENGTH;
1148 }
1149
Dominik Geyerb46acba2008-05-16 12:55:55 +00001150 /* if opcode-type requires an address */
1151 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1152 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001153 addr = (writearr[1] << 16) |
1154 (writearr[2] << 8) | (writearr[3] << 0);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001155 if (addr < ichspi_bbar) {
1156 msg_perr("%s: Address 0x%06x below allowed "
1157 "range 0x%06x-0xffffff\n", __func__,
1158 addr, ichspi_bbar);
1159 return SPI_INVALID_ADDRESS;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001160 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001161 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001162
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001163 /* Translate read/write array/count.
1164 * The maximum data length is identical for the maximum read length and
1165 * for the maximum write length excluding opcode and address. Opcode and
1166 * address are stored in separate registers, not in the data registers
1167 * and are thus not counted towards data length. The only exception
1168 * applies if the opcode definition (un)intentionally classifies said
1169 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001170 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001171 data = (uint8_t *) (writearr + 1);
1172 count = writecnt - 1;
1173 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1174 data = (uint8_t *) (writearr + 4);
1175 count = writecnt - 4;
1176 } else {
1177 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001178 count = readcnt;
1179 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001180
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001181 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001182 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001183 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1184 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1185 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1186 msg_pdbg("at address 0x%06x ", addr);
1187 }
1188 msg_pdbg("(payload length was %d).\n", count);
1189
1190 /* Print out the data array if it contains data to write.
1191 * Errors are detected before the received data is read back into
1192 * the array so it won't make sense to print it then. */
1193 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1194 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1195 int i;
1196 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001197 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001198 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1199 }
1200 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001201 }
1202
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001203 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001204}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001205
Stefan Tauner50e7c602011-11-08 10:55:54 +00001206static struct hwseq_data {
1207 uint32_t size_comp0;
1208 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001209 uint32_t addr_mask;
1210 bool only_4k;
1211 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001212} hwseq_data;
1213
Nico Huberd54e4f42017-03-23 23:45:47 +01001214/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001215static void ich_hwseq_set_addr(uint32_t addr)
1216{
Nico Huberd54e4f42017-03-23 23:45:47 +01001217 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1218 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001219}
1220
1221/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1222 * of the block containing this address. May return nonsense if the address is
1223 * not valid. The erase block size for a specific address depends on the flash
1224 * partition layout as specified by FPB and the partition properties as defined
1225 * by UVSCC and LVSCC respectively. An alternative to implement this method
1226 * would be by querying FPB and the respective VSCC register directly.
1227 */
1228static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1229{
Nico Huberd54e4f42017-03-23 23:45:47 +01001230 if (hwseq_data.only_4k) {
1231 return 4 * 1024;
1232 } else {
1233 uint8_t enc_berase;
1234 static const uint32_t dec_berase[4] = {
1235 256,
1236 4 * 1024,
1237 8 * 1024,
1238 64 * 1024
1239 };
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001240
Nico Huberd54e4f42017-03-23 23:45:47 +01001241 ich_hwseq_set_addr(addr);
1242 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1243 return dec_berase[enc_berase];
1244 }
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001245}
1246
1247/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1248 Resets all error flags in HSFS.
1249 Returns 0 if the cycle completes successfully without errors within
1250 timeout us, 1 on errors. */
1251static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1252 unsigned int len)
1253{
1254 uint16_t hsfs;
1255 uint32_t addr;
1256
1257 timeout /= 8; /* scale timeout duration to counter */
1258 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1259 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1260 --timeout) {
1261 programmer_delay(8);
1262 }
1263 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1264 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001265 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001266 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001267 "0x%08x (= 0x%08x + %d)!\n",
1268 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001269 prettyprint_ich9_reg_hsfs(hsfs);
1270 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1271 return 1;
1272 }
1273
1274 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001275 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001276 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001277 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001278 addr, addr + len - 1, addr, len - 1);
1279 prettyprint_ich9_reg_hsfs(hsfs);
1280 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1281 return 1;
1282 }
1283 return 0;
1284}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001285
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001286static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001287{
1288 uint32_t total_size, boundary;
1289 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1290 struct block_eraser *eraser;
1291
1292 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001293 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001294 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1295 if (hwseq_data.size_comp1 != 0)
1296 msg_cdbg("s with a combined");
1297 else
1298 msg_cdbg(" with a");
1299 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001300 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001301
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001302 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001303 if (!hwseq_data.only_4k)
1304 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1305 else
1306 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001307 size_high = total_size - boundary;
1308 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1309
1310 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001311 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001312 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1313 eraser->eraseblocks[0].size = erase_size_high;
1314 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001315 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001316 size_high / erase_size_high, erase_size_high);
1317 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001318 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001319 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001320 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001321 size_low = total_size - size_high;
1322 erase_size_low = ich_hwseq_get_erase_block_size(0);
1323
1324 eraser->eraseblocks[0].size = erase_size_low;
1325 eraser->eraseblocks[0].count = size_low / erase_size_low;
1326 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1327 0, size_low-1);
1328 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1329 size_low / erase_size_low, erase_size_low);
1330
1331 eraser->eraseblocks[1].size = erase_size_high;
1332 eraser->eraseblocks[1].count = size_high / erase_size_high;
1333 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001334 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001335 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1336 size_high / erase_size_high, erase_size_high);
1337 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001338 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001339 return 1;
1340}
1341
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001342static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1343 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001344{
1345 uint32_t erase_block;
1346 uint16_t hsfc;
1347 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1348
1349 erase_block = ich_hwseq_get_erase_block_size(addr);
1350 if (len != erase_block) {
1351 msg_cerr("Erase block size for address 0x%06x is %d B, "
1352 "but requested erase block size is %d B. "
1353 "Not erasing anything.\n", addr, erase_block, len);
1354 return -1;
1355 }
1356
1357 /* Although the hardware supports this (it would erase the whole block
1358 * containing the address) we play safe here. */
1359 if (addr % erase_block != 0) {
1360 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1361 "block boundary (any multiple of %d). "
1362 "Not erasing anything.\n", addr, erase_block);
1363 return -1;
1364 }
1365
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001366 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001367 msg_perr("Request to erase some inaccessible memory address(es)"
1368 " (addr=0x%x, len=%d). "
1369 "Not erasing anything.\n", addr, len);
1370 return -1;
1371 }
1372
1373 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001374 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001375
1376 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1377 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1378
1379 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001380 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001381 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1382 hsfc |= HSFC_FGO; /* start */
1383 msg_pdbg("HSFC used for block erasing: ");
1384 prettyprint_ich9_reg_hsfc(hsfc);
1385 REGWRITE16(ICH9_REG_HSFC, hsfc);
1386
1387 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1388 return -1;
1389 return 0;
1390}
1391
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001392static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1393 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001394{
1395 uint16_t hsfc;
1396 uint16_t timeout = 100 * 60;
1397 uint8_t block_len;
1398
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001399 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001400 msg_perr("Request to read from an inaccessible memory address "
1401 "(addr=0x%x, len=%d).\n", addr, len);
1402 return -1;
1403 }
1404
1405 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1406 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1407 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1408
1409 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001410 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001411 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001412 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1413 block_len = min(block_len, 256 - (addr & 0xFF));
1414
Stefan Tauner50e7c602011-11-08 10:55:54 +00001415 ich_hwseq_set_addr(addr);
1416 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001417 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001418 hsfc &= ~HSFC_FDBC; /* clear byte count */
1419 /* set byte count */
1420 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1421 hsfc |= HSFC_FGO; /* start */
1422 REGWRITE16(ICH9_REG_HSFC, hsfc);
1423
1424 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1425 return 1;
1426 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1427 addr += block_len;
1428 buf += block_len;
1429 len -= block_len;
1430 }
1431 return 0;
1432}
1433
Mark Marshallf20b7be2014-05-09 21:16:21 +00001434static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001435{
1436 uint16_t hsfc;
1437 uint16_t timeout = 100 * 60;
1438 uint8_t block_len;
1439
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001440 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001441 msg_perr("Request to write to an inaccessible memory address "
1442 "(addr=0x%x, len=%d).\n", addr, len);
1443 return -1;
1444 }
1445
1446 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1447 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1448 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1449
1450 while (len > 0) {
1451 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001452 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001453 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001454 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1455 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001456 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1457 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001458 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001459 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1460 hsfc &= ~HSFC_FDBC; /* clear byte count */
1461 /* set byte count */
1462 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1463 hsfc |= HSFC_FGO; /* start */
1464 REGWRITE16(ICH9_REG_HSFC, hsfc);
1465
1466 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1467 return -1;
1468 addr += block_len;
1469 buf += block_len;
1470 len -= block_len;
1471 }
1472 return 0;
1473}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001474
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001475static int ich_spi_send_multicommand(struct flashctx *flash,
1476 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001477{
1478 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001479 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001480 int oppos, preoppos;
1481 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001482 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001483 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001484 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1485 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001486 if ((oppos == -1) && (preoppos != -1)) {
1487 /* Current command is listed as preopcode in
1488 * ICH struct OPCODES, but next command is not
1489 * listed as opcode in that struct.
1490 * Check for command sanity, then
1491 * try to reprogram the ICH opcode list.
1492 */
1493 if (find_preop(curopcodes,
1494 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001495 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001496 "preopcodes 0x%02x and 0x%02x, "
1497 "ignoring the first.\n",
1498 __func__, cmds->writearr[0],
1499 (cmds + 1)->writearr[0]);
1500 continue;
1501 }
1502 /* If the chipset is locked down, we'll fail
1503 * during execution of the next command anyway.
1504 * No need to bother with fixups.
1505 */
1506 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001507 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1508 if (oppos == -1)
1509 continue;
1510 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001511 continue;
1512 }
1513 }
1514 if ((oppos != -1) && (preoppos != -1)) {
1515 /* Current command is listed as preopcode in
1516 * ICH struct OPCODES and next command is listed
1517 * as opcode in that struct. Match them up.
1518 */
1519 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001520 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001521 }
1522 /* If none of the above if-statements about oppos or
1523 * preoppos matched, this is a normal opcode.
1524 */
1525 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001526 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001527 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001528 /* Reset the type of all opcodes to non-atomic. */
1529 for (i = 0; i < 8; i++)
1530 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001531 }
1532 return ret;
1533}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001534
Michael Karchera4448d92010-07-22 18:04:15 +00001535#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1536#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1537#define ICH_BRWA(x) ((x >> 8) & 0xff)
1538#define ICH_BRRA(x) ((x >> 0) & 0xff)
1539
Stefan Tauner5210e722012-02-16 01:13:00 +00001540/* returns 0 if region is unused or r/w */
1541static int ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001542{
Mathias Krausea60faab2011-01-17 07:50:42 +00001543 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001544 "locked", "read-only", "write-only", "read-write"
1545 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001546 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001547 "Flash Descriptor", "BIOS", "Management Engine",
1548 "Gigabit Ethernet", "Platform Data"
1549 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001550 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1551
Michael Karchera4448d92010-07-22 18:04:15 +00001552 uint32_t base, limit;
1553 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1554 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001555 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001556 uint32_t freg = mmio_readl(ich_spibar + offset);
1557
Michael Karchera4448d92010-07-22 18:04:15 +00001558 base = ICH_FREG_BASE(freg);
1559 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001560 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001561 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001562 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001563 offset, freg, i, region_name);
Stefan Tauner5210e722012-02-16 01:13:00 +00001564 return 0;
1565 }
1566 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1567 if (rwperms == 0x3) {
1568 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001569 region_name, base, limit, access_names[rwperms]);
Stefan Tauner5210e722012-02-16 01:13:00 +00001570 return 0;
Michael Karchera4448d92010-07-22 18:04:15 +00001571 }
1572
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001573 msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001574 region_name, base, limit, access_names[rwperms]);
Stefan Tauner5210e722012-02-16 01:13:00 +00001575 return 1;
Michael Karchera4448d92010-07-22 18:04:15 +00001576}
1577
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001578 /* In contrast to FRAP and the master section of the descriptor the bits
1579 * in the PR registers have an inverted meaning. The bits in FRAP
1580 * indicate read and write access _grant_. Here they indicate read
1581 * and write _protection_ respectively. If both bits are 0 the address
1582 * bits are ignored.
1583 */
1584#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1585 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1586
Stefan Tauner5210e722012-02-16 01:13:00 +00001587/* returns 0 if range is unused (i.e. r/w) */
Nico Huberd54e4f42017-03-23 23:45:47 +01001588static int ich9_handle_pr(const size_t reg_pr0, int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001589{
Stefan Tauner5210e722012-02-16 01:13:00 +00001590 static const char *const access_names[3] = {
1591 "locked", "read-only", "write-only"
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001592 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001593 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001594 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001595 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001596
Nico Huberd54e4f42017-03-23 23:45:47 +01001597 /* From 5 on we have GPR registers and start from 0 again. */
1598 const char *const prefix = i >= 5 ? "G" : "";
1599 if (i >= 5)
1600 i -= 5;
1601
Stefan Tauner5210e722012-02-16 01:13:00 +00001602 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001603 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001604 return 0;
1605 }
1606
1607 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001608 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001609 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Stefan Tauner5210e722012-02-16 01:13:00 +00001610 return 1;
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001611}
1612
Stefan Tauner75da80c2011-09-17 22:21:55 +00001613/* Set/Clear the read and write protection enable bits of PR register @i
1614 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001615static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001616{
Nico Huberd54e4f42017-03-23 23:45:47 +01001617 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001618 uint32_t old = mmio_readl(addr);
1619 uint32_t new;
1620
1621 msg_gspew("PR%u is 0x%08x", i, old);
1622 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1623 if (read_prot)
1624 new |= (1 << PR_RP_OFF);
1625 if (write_prot)
1626 new |= (1 << PR_WP_OFF);
1627 if (old == new) {
1628 msg_gspew(" already.\n");
1629 return;
1630 }
1631 msg_gspew(", trying to set it to 0x%08x ", new);
1632 rmmio_writel(new, addr);
1633 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1634}
1635
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001636static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001637 .type = SPI_CONTROLLER_ICH7,
1638 .max_data_read = 64,
1639 .max_data_write = 64,
1640 .command = ich_spi_send_command,
1641 .multicommand = ich_spi_send_multicommand,
1642 .read = default_spi_read,
1643 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001644 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001645};
1646
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001647static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001648 .type = SPI_CONTROLLER_ICH9,
1649 .max_data_read = 64,
1650 .max_data_write = 64,
1651 .command = ich_spi_send_command,
1652 .multicommand = ich_spi_send_multicommand,
1653 .read = default_spi_read,
1654 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001655 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001656};
1657
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001658static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001659 .max_data_read = 64,
1660 .max_data_write = 64,
1661 .probe = ich_hwseq_probe,
1662 .read = ich_hwseq_read,
1663 .write = ich_hwseq_write,
1664 .erase = ich_hwseq_block_erase,
1665};
1666
Nico Huber560111e2017-04-26 12:27:17 +02001667int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001668{
1669 int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001670 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001671 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001672 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001673 int ich_spi_force = 0;
1674 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001675 int desc_valid = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001676 struct ich_descriptors desc = {{ 0 }};
1677 enum ich_spi_mode {
1678 ich_auto,
1679 ich_hwseq,
1680 ich_swseq
1681 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001682 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001683
Stefan Taunera8d838d2011-11-06 23:51:09 +00001684 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001685 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001686
Nico Huberd54e4f42017-03-23 23:45:47 +01001687 /* Moving registers / bits */
1688 if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
1689 num_freg = 10;
1690 num_pr = 6;
1691 reg_pr0 = PCH100_REG_FPR0;
1692 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1693 swseq_data.reg_preop = PCH100_REG_PREOP;
1694 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1695 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1696 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1697 hwseq_data.only_4k = true;
1698 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
1699 } else {
1700 num_freg = 5;
1701 num_pr = 5;
1702 reg_pr0 = ICH9_REG_PR0;
1703 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1704 swseq_data.reg_preop = ICH9_REG_PREOP;
1705 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1706 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1707 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1708 hwseq_data.only_4k = false;
1709 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
1710 }
1711
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001712 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001713 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001714 case CHIPSET_TUNNEL_CREEK:
1715 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001716 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1717 mmio_readw(ich_spibar + 0));
1718 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1719 mmio_readw(ich_spibar + 2));
1720 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1721 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001722 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1723 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1724 ichspi_bbar);
1725 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1726 mmio_readw(ich_spibar + 0x54));
1727 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1728 mmio_readw(ich_spibar + 0x56));
1729 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1730 mmio_readl(ich_spibar + 0x58));
1731 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1732 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001733 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001734 int offs;
1735 offs = 0x60 + (i * 4);
1736 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1737 mmio_readl(ich_spibar + offs), i);
1738 }
Michael Karchera4448d92010-07-22 18:04:15 +00001739 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001740 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001741 ichspi_lock = 1;
1742 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001743 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001744 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001745 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001746 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001747 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001748 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001749 arg = extract_programmer_param("ich_spi_mode");
1750 if (arg && !strcmp(arg, "hwseq")) {
1751 ich_spi_mode = ich_hwseq;
1752 msg_pspew("user selected hwseq\n");
1753 } else if (arg && !strcmp(arg, "swseq")) {
1754 ich_spi_mode = ich_swseq;
1755 msg_pspew("user selected swseq\n");
1756 } else if (arg && !strcmp(arg, "auto")) {
1757 msg_pspew("user selected auto\n");
1758 ich_spi_mode = ich_auto;
1759 } else if (arg && !strlen(arg)) {
1760 msg_perr("Missing argument for ich_spi_mode.\n");
1761 free(arg);
1762 return ERROR_FATAL;
1763 } else if (arg) {
1764 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1765 arg);
1766 free(arg);
1767 return ERROR_FATAL;
1768 }
1769 free(arg);
1770
Stefan Tauner5210e722012-02-16 01:13:00 +00001771 arg = extract_programmer_param("ich_spi_force");
1772 if (arg && !strcmp(arg, "yes")) {
1773 ich_spi_force = 1;
1774 msg_pspew("ich_spi_force enabled.\n");
1775 } else if (arg && !strlen(arg)) {
1776 msg_perr("Missing argument for ich_spi_force.\n");
1777 free(arg);
1778 return ERROR_FATAL;
1779 } else if (arg) {
1780 msg_perr("Unknown argument for ich_spi_force: \"%s\" "
1781 "(not \"yes\").\n", arg);
1782 free(arg);
1783 return ERROR_FATAL;
1784 }
1785 free(arg);
1786
Stefan Tauner29c80832011-06-12 08:14:10 +00001787 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001788 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001789 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001790 if (tmp2 & HSFS_FLOCKDN) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001791 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001792 ichspi_lock = 1;
1793 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001794 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001795 desc_valid = 1;
1796 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001797 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1798 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1799 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001800 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001801
Stefan Taunerf382e352011-11-08 11:55:24 +00001802 if (desc_valid) {
1803 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1804 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1805 prettyprint_ich9_reg_hsfc(tmp2);
1806 }
Michael Karchera4448d92010-07-22 18:04:15 +00001807
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001808 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001809 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001810
Nico Huberd54e4f42017-03-23 23:45:47 +01001811 if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
1812 const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1813 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock);
1814 prettyprint_pch100_reg_dlock(dlock);
1815 }
1816
Stefan Taunerf382e352011-11-08 11:55:24 +00001817 if (desc_valid) {
1818 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1819 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1820 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1821 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1822 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1823 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1824
Stefan Tauner5210e722012-02-16 01:13:00 +00001825 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001826 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001827 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001828 if (ich_spi_rw_restricted)
1829 msg_pwarn("Not all flash regions are freely accessible by flashrom. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001830 "most likely\ndue to an active ME. Please see "
1831 "https://flashrom.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001832 }
Michael Karchera4448d92010-07-22 18:04:15 +00001833
Stefan Taunereb582572012-09-21 12:52:50 +00001834 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001835 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001836 /* if not locked down try to disable PR locks first */
1837 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001838 ich9_set_pr(reg_pr0, i, 0, 0);
1839 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001840 }
1841
1842 if (ich_spi_rw_restricted) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001843 if (!ich_spi_force)
1844 programmer_may_write = 0;
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001845 msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n"
1846 "support with the ich_spi_force programmer option, but you will most likely\n"
1847 "harm your hardware! If you force flashrom you will get no support if\n"
1848 "something breaks. On a few mainboards it is possible to enable write\n"
1849 "access by setting a jumper (see its documentation or the board itself).\n");
Stefan Tauner5210e722012-02-16 01:13:00 +00001850 if (ich_spi_force)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001851 msg_pinfo("Continuing with write support because the user forced us to!\n");
Stefan Tauner5210e722012-02-16 01:13:00 +00001852 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001853
Nico Huberd54e4f42017-03-23 23:45:47 +01001854 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1855 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001856 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001857 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001858 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001859 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001860 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001861 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001862 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001863
Nico Huberd54e4f42017-03-23 23:45:47 +01001864 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1865 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1866 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1867 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1868 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1869 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1870 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1871 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Stefan Taunerf382e352011-11-08 11:55:24 +00001872 if (ich_generation == CHIPSET_ICH8 && desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001873 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1874 msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
1875 msg_pdbg("VSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001876 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Nico Huberd54e4f42017-03-23 23:45:47 +01001877 } else if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) {
Duncan Laurie4095ed72014-08-20 15:39:32 +00001878 if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) {
1879 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
1880 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1881 ichspi_bbar);
1882 ich_set_bbar(0);
1883 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001884
Stefan Taunerf382e352011-11-08 11:55:24 +00001885 if (desc_valid) {
1886 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
1887 msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
1888 msg_pdbg("LVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001889 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001890
Stefan Taunerf382e352011-11-08 11:55:24 +00001891 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
1892 msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
1893 msg_pdbg("UVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001894 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
Stefan Tauner1e146392011-09-15 23:52:55 +00001895
Stefan Taunerf382e352011-11-08 11:55:24 +00001896 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1897 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1898 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001899 }
1900
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001901 if (desc_valid) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100