blob: 09da5795cef1b405f0c1f06ca28c4594eaa95137 [file] [log] [blame]
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000014 */
15
16#ifndef __SPI_H__
17#define __SPI_H__ 1
18
19/*
20 * Contains the generic SPI headers
21 */
22
Nico Huber0ecbacb2017-10-14 16:50:43 +020023#define JEDEC_MAX_ADDR_LEN 0x04
24
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000025/* Read Electronic ID */
26#define JEDEC_RDID 0x9f
27#define JEDEC_RDID_OUTSIZE 0x01
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000028/* INSIZE may be 0x04 for some chips*/
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000029#define JEDEC_RDID_INSIZE 0x03
30
Konstantin Grudnev3d8868c2019-07-23 00:48:54 +030031/* Some ST M95X model */
32#define ST_M95_RDID 0x83
33#define ST_M95_RDID_3BA_OUTSIZE 0x04 /* 8b op, 24bit addr where size >64KiB */
34#define ST_M95_RDID_2BA_OUTSIZE 0x03 /* 8b op, 16bit addr where size <=64KiB */
35#define ST_M95_RDID_OUTSIZE_MAX 0x04 /* ST_M95_RDID_3BA_OUTSIZE */
36#define ST_M95_RDID_INSIZE 0x03
37
Stefan Tauner57794ac2012-12-29 15:04:20 +000038/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */
39#define AT25F_RDID 0x15 /* 0x15 or 0x1d */
40#define AT25F_RDID_OUTSIZE 0x01
41#define AT25F_RDID_INSIZE 0x02
Carl-Daniel Hailfinger0faf03e2008-11-28 23:47:55 +000042
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +000043/* Read Electronic Manufacturer Signature */
44#define JEDEC_REMS 0x90
45#define JEDEC_REMS_OUTSIZE 0x04
46#define JEDEC_REMS_INSIZE 0x02
47
Stefan Taunerac1b4c82012-02-17 14:51:04 +000048/* Read Serial Flash Discoverable Parameters (SFDP) */
49#define JEDEC_SFDP 0x5a
50#define JEDEC_SFDP_OUTSIZE 0x05 /* 8b op, 24b addr, 8b dummy */
51/* JEDEC_SFDP_INSIZE : any length */
52
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000053/* Read Electronic Signature */
54#define JEDEC_RES 0xab
55#define JEDEC_RES_OUTSIZE 0x04
Carl-Daniel Hailfingerdc1cda12010-05-28 17:07:57 +000056/* INSIZE may be 0x02 for some chips*/
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +000057#define JEDEC_RES_INSIZE 0x01
58
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000059/* Write Enable */
60#define JEDEC_WREN 0x06
61#define JEDEC_WREN_OUTSIZE 0x01
62#define JEDEC_WREN_INSIZE 0x00
63
64/* Write Disable */
65#define JEDEC_WRDI 0x04
66#define JEDEC_WRDI_OUTSIZE 0x01
67#define JEDEC_WRDI_INSIZE 0x00
68
69/* Chip Erase 0x60 is supported by Macronix/SST chips. */
70#define JEDEC_CE_60 0x60
71#define JEDEC_CE_60_OUTSIZE 0x01
72#define JEDEC_CE_60_INSIZE 0x00
73
Stefan Tauner3c0fcd02012-09-21 12:46:56 +000074/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
75#define JEDEC_CE_62 0x62
76#define JEDEC_CE_62_OUTSIZE 0x01
77#define JEDEC_CE_62_INSIZE 0x00
78
Peter Stugef83221b2008-07-07 06:38:51 +000079/* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000080#define JEDEC_CE_C7 0xc7
81#define JEDEC_CE_C7_OUTSIZE 0x01
82#define JEDEC_CE_C7_INSIZE 0x00
83
Stefan Tauner94b39b42012-10-27 00:06:02 +000084/* Block Erase 0x50 is supported by Atmel AT26DF chips. */
85#define JEDEC_BE_50 0x50
86#define JEDEC_BE_50_OUTSIZE 0x04
87#define JEDEC_BE_50_INSIZE 0x00
88
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +000089/* Block Erase 0x52 is supported by SST and old Atmel chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +000090#define JEDEC_BE_52 0x52
91#define JEDEC_BE_52_OUTSIZE 0x04
92#define JEDEC_BE_52_INSIZE 0x00
93
Stefan Tauner94b39b42012-10-27 00:06:02 +000094/* Block Erase 0x81 is supported by Atmel AT26DF chips. */
95#define JEDEC_BE_81 0x81
96#define JEDEC_BE_81_OUTSIZE 0x04
97#define JEDEC_BE_81_INSIZE 0x00
98
Nikolay Nikolaev6f59b0b2013-06-28 21:29:51 +000099/* Block Erase 0xc4 is supported by Micron chips. */
100#define JEDEC_BE_C4 0xc4
101#define JEDEC_BE_C4_OUTSIZE 0x04
102#define JEDEC_BE_C4_INSIZE 0x00
103
Nico Huber9dc3d8d2020-04-27 22:51:49 +0000104/* Block Erase 0xd8 is supported by EON/Macronix chips. */
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000105#define JEDEC_BE_D8 0xd8
106#define JEDEC_BE_D8_OUTSIZE 0x04
107#define JEDEC_BE_D8_INSIZE 0x00
108
Sean Nelson5643c072010-01-19 03:23:07 +0000109/* Block Erase 0xd7 is supported by PMC chips. */
110#define JEDEC_BE_D7 0xd7
111#define JEDEC_BE_D7_OUTSIZE 0x04
112#define JEDEC_BE_D7_INSIZE 0x00
113
Nikolai Artemievadbae0e2020-10-06 16:59:51 +1100114/* Block Erase 0xdc is supported by Spansion chips, takes 4 byte address */
115#define JEDEC_BE_DC 0xdc
116#define JEDEC_BE_DC_OUTSIZE 0x05
117#define JEDEC_BE_DC_INSIZE 0x00
118
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000119/* Sector Erase 0x20 is supported by Macronix/SST chips. */
120#define JEDEC_SE 0x20
121#define JEDEC_SE_OUTSIZE 0x04
122#define JEDEC_SE_INSIZE 0x00
123
Nikolay Nikolaev579f1e02013-06-28 21:28:37 +0000124/* Page Erase 0xDB */
125#define JEDEC_PE 0xDB
126#define JEDEC_PE_OUTSIZE 0x04
127#define JEDEC_PE_INSIZE 0x00
128
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000129/* Read Status Register */
130#define JEDEC_RDSR 0x05
131#define JEDEC_RDSR_OUTSIZE 0x01
132#define JEDEC_RDSR_INSIZE 0x01
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000133
134/* Status Register Bits */
135#define SPI_SR_WIP (0x01 << 0)
136#define SPI_SR_WEL (0x01 << 1)
Nikolai Artemievadbae0e2020-10-06 16:59:51 +1100137#define SPI_SR_ERA_ERR (0x01 << 5)
Stefan Tauner5e695ab2012-05-06 17:03:40 +0000138#define SPI_SR_AAI (0x01 << 6)
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000139
Jason Wanga3f04be2008-11-28 21:36:51 +0000140/* Write Status Enable */
141#define JEDEC_EWSR 0x50
142#define JEDEC_EWSR_OUTSIZE 0x01
143#define JEDEC_EWSR_INSIZE 0x00
144
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000145/* Write Status Register */
146#define JEDEC_WRSR 0x01
147#define JEDEC_WRSR_OUTSIZE 0x02
148#define JEDEC_WRSR_INSIZE 0x00
149
Nico Huber7e3c81a2017-10-14 18:56:50 +0200150/* Enter 4-byte Address Mode */
151#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
152
153/* Exit 4-byte Address Mode */
154#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9
155
156/* Write Extended Address Register */
157#define JEDEC_WRITE_EXT_ADDR_REG 0xC5
158
159/* Read Extended Address Register */
160#define JEDEC_READ_EXT_ADDR_REG 0xC8
161
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000162/* Read the memory */
163#define JEDEC_READ 0x03
164#define JEDEC_READ_OUTSIZE 0x04
165/* JEDEC_READ_INSIZE : any length */
166
Nico Huber93db6e12018-09-30 01:18:43 +0200167/* Read the memory (with delay after sending address) */
168#define JEDEC_READ_FAST 0x0b
169
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000170/* Write memory byte */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000171#define JEDEC_BYTE_PROGRAM 0x02
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000172#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
173#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
174
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000175/* Write AAI word (SST25VF080B) */
Carl-Daniel Hailfingerd99b8d32010-07-29 16:32:24 +0000176#define JEDEC_AAI_WORD_PROGRAM 0xad
177#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06
178#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x03
179#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00
Carl-Daniel Hailfinger9c62d112010-06-20 10:41:35 +0000180
Nico Huber7e3c81a2017-10-14 18:56:50 +0200181/* Read the memory with 4-byte address
182 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
183#define JEDEC_READ_4BA 0x13
184
Nico Huber93db6e12018-09-30 01:18:43 +0200185/* Read the memory with 4-byte address (and delay after sending address)
186 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
187#define JEDEC_READ_4BA_FAST 0x0c
188
Nico Huber7e3c81a2017-10-14 18:56:50 +0200189/* Write memory byte with 4-byte address
190 From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
191#define JEDEC_BYTE_PROGRAM_4BA 0x12
192
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000193/* Error codes */
Carl-Daniel Hailfinger5cca01f2009-11-24 00:20:03 +0000194#define SPI_GENERIC_ERROR -1
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000195#define SPI_INVALID_OPCODE -2
196#define SPI_INVALID_ADDRESS -3
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000197#define SPI_INVALID_LENGTH -4
Carl-Daniel Hailfingerfd7075a2010-07-29 13:09:18 +0000198#define SPI_FLASHROM_BUG -5
Carl-Daniel Hailfingereb0e7fc2010-08-18 15:12:43 +0000199#define SPI_PROGRAMMER_ERROR -6
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000200
Edward O'Callaghan3b129452020-05-14 15:19:42 +1000201void clear_spi_id_cache(void);
202
Carl-Daniel Hailfingerd6cbf762008-05-13 14:58:23 +0000203#endif /* !__SPI_H__ */