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Joerg Fischer52a15492010-05-21 22:28:19 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Joerg Fischer <turboj@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000021#if defined(__i386__) || defined(__x86_64__)
22
Joerg Fischer52a15492010-05-21 22:28:19 +000023#include <stdlib.h>
Joerg Fischer52a15492010-05-21 22:28:19 +000024#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000025#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000026#include "hwaccess.h"
Joerg Fischer52a15492010-05-21 22:28:19 +000027
28#define PCI_VENDOR_ID_REALTEK 0x10ec
29#define PCI_VENDOR_ID_SMC1211 0x1113
30
31#define BIOS_ROM_ADDR 0xD4
32#define BIOS_ROM_DATA 0xD7
33
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000034const struct pcidev_status nics_realtek[] = {
Uwe Hermann829ed842010-05-24 17:39:14 +000035 {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"},
Uwe Hermann829ed842010-05-24 17:39:14 +000036 {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */
37 {},
Joerg Fischer52a15492010-05-21 22:28:19 +000038};
39
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000040static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,
41 chipaddr addr);
42static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,
43 const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000044static const struct par_programmer par_programmer_nicrealtek = {
45 .chip_readb = nicrealtek_chip_readb,
46 .chip_readw = fallback_chip_readw,
47 .chip_readl = fallback_chip_readl,
48 .chip_readn = fallback_chip_readn,
49 .chip_writeb = nicrealtek_chip_writeb,
50 .chip_writew = fallback_chip_writew,
51 .chip_writel = fallback_chip_writel,
52 .chip_writen = fallback_chip_writen,
53};
54
David Hendricks8bb20212011-06-14 01:35:36 +000055static int nicrealtek_shutdown(void *data)
56{
57 /* FIXME: We forgot to disable software access again. */
58 pci_cleanup(pacc);
59 release_io_perms();
60 return 0;
61}
62
Joerg Fischer52a15492010-05-21 22:28:19 +000063int nicrealtek_init(void)
64{
65 get_io_perms();
Uwe Hermann829ed842010-05-24 17:39:14 +000066
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000067 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
Uwe Hermann829ed842010-05-24 17:39:14 +000068
David Hendricks8bb20212011-06-14 01:35:36 +000069 if (register_shutdown(nicrealtek_shutdown, NULL))
70 return 1;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000071
72 register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL);
73
Joerg Fischer52a15492010-05-21 22:28:19 +000074 return 0;
75}
76
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000077static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val,
78 chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000079{
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000080 /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
81 * enable software access.
82 */
Uwe Hermann829ed842010-05-24 17:39:14 +000083 OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
84 io_base_addr + BIOS_ROM_ADDR);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000085 /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
86 * enable software access.
87 */
Uwe Hermann829ed842010-05-24 17:39:14 +000088 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
89 io_base_addr + BIOS_ROM_ADDR);
Joerg Fischer52a15492010-05-21 22:28:19 +000090}
91
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000092static uint8_t nicrealtek_chip_readb(const struct flashctx *flash,
93 const chipaddr addr)
Joerg Fischer52a15492010-05-21 22:28:19 +000094{
Uwe Hermann829ed842010-05-24 17:39:14 +000095 uint8_t val;
Joerg Fischer52a15492010-05-21 22:28:19 +000096
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +000097 /* FIXME: Can we skip reading the old data and simply use 0? */
98 /* Read old data. */
Uwe Hermann829ed842010-05-24 17:39:14 +000099 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000100 /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
101 * enable software access.
102 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000103 OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
104 io_base_addr + BIOS_ROM_ADDR);
105
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000106 /* Read new data. */
Uwe Hermann829ed842010-05-24 17:39:14 +0000107 val = INB(io_base_addr + BIOS_ROM_DATA);
Carl-Daniel Hailfinger2eda3912010-06-14 14:18:37 +0000108 /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
109 * enable software access.
110 */
Uwe Hermann829ed842010-05-24 17:39:14 +0000111 OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
112 io_base_addr + BIOS_ROM_ADDR);
113
114 return val;
Joerg Fischer52a15492010-05-21 22:28:19 +0000115}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000116
117#else
118#error PCI port I/O access is not supported on this architecture yet.
119#endif