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Uwe Hermann2bc98f62009-09-30 18:29:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <stdlib.h>
22#include <string.h>
Uwe Hermann2bc98f62009-09-30 18:29:55 +000023#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000024#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000025#include "hwaccess.h"
Uwe Hermann2bc98f62009-09-30 18:29:55 +000026
27#define PCI_VENDOR_ID_NVIDIA 0x10de
28
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +000029/* Mask to restrict flash accesses to a 128kB memory window.
30 * FIXME: Is this size a one-fits-all or card dependent?
31 */
32#define GFXNVIDIA_MEMMAP_MASK ((1 << 17) - 1)
David Hendricks8bb20212011-06-14 01:35:36 +000033#define GFXNVIDIA_MEMMAP_SIZE (16 * 1024 * 1024)
Carl-Daniel Hailfingerfb2c4c32010-07-17 22:42:33 +000034
Uwe Hermann2bc98f62009-09-30 18:29:55 +000035uint8_t *nvidia_bar;
36
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000037const struct pcidev_status gfx_nvidia[] = {
Michael Karcher84486392010-02-24 00:04:40 +000038 {0x10de, 0x0010, NT, "NVIDIA", "Mutara V08 [NV2]" },
39 {0x10de, 0x0018, NT, "NVIDIA", "RIVA 128" },
40 {0x10de, 0x0020, NT, "NVIDIA", "RIVA TNT" },
41 {0x10de, 0x0028, NT, "NVIDIA", "RIVA TNT2/TNT2 Pro" },
42 {0x10de, 0x0029, NT, "NVIDIA", "RIVA TNT2 Ultra" },
43 {0x10de, 0x002c, NT, "NVIDIA", "Vanta/Vanta LT" },
44 {0x10de, 0x002d, OK, "NVIDIA", "RIVA TNT2 Model 64/Model 64 Pro" },
45 {0x10de, 0x00a0, NT, "NVIDIA", "Aladdin TNT2" },
46 {0x10de, 0x0100, NT, "NVIDIA", "GeForce 256" },
47 {0x10de, 0x0101, NT, "NVIDIA", "GeForce DDR" },
48 {0x10de, 0x0103, NT, "NVIDIA", "Quadro" },
49 {0x10de, 0x0110, NT, "NVIDIA", "GeForce2 MX" },
50 {0x10de, 0x0111, NT, "NVIDIA", "GeForce2 MX" },
51 {0x10de, 0x0112, NT, "NVIDIA", "GeForce2 GO" },
52 {0x10de, 0x0113, NT, "NVIDIA", "Quadro2 MXR" },
53 {0x10de, 0x0150, NT, "NVIDIA", "GeForce2 GTS/Pro" },
54 {0x10de, 0x0151, NT, "NVIDIA", "GeForce2 GTS" },
55 {0x10de, 0x0152, NT, "NVIDIA", "GeForce2 Ultra" },
56 {0x10de, 0x0153, NT, "NVIDIA", "Quadro2 Pro" },
57 {0x10de, 0x0200, NT, "NVIDIA", "GeForce 3 nFX" },
58 {0x10de, 0x0201, NT, "NVIDIA", "GeForce 3 nFX" },
59 {0x10de, 0x0202, NT, "NVIDIA", "GeForce 3 nFX Ultra" },
60 {0x10de, 0x0203, NT, "NVIDIA", "Quadro 3 DDC" },
Uwe Hermann2bc98f62009-09-30 18:29:55 +000061
62 {},
63};
64
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000065static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
66 chipaddr addr);
67static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
68 const chipaddr addr);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000069static const struct par_programmer par_programmer_gfxnvidia = {
70 .chip_readb = gfxnvidia_chip_readb,
71 .chip_readw = fallback_chip_readw,
72 .chip_readl = fallback_chip_readl,
73 .chip_readn = fallback_chip_readn,
74 .chip_writeb = gfxnvidia_chip_writeb,
75 .chip_writew = fallback_chip_writew,
76 .chip_writel = fallback_chip_writel,
77 .chip_writen = fallback_chip_writen,
78};
79
David Hendricks8bb20212011-06-14 01:35:36 +000080static int gfxnvidia_shutdown(void *data)
81{
82 physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE);
83 /* Flash interface access is disabled (and screen enabled) automatically
84 * by PCI restore.
85 */
86 pci_cleanup(pacc);
87 release_io_perms();
88 return 0;
89}
90
Uwe Hermann2bc98f62009-09-30 18:29:55 +000091int gfxnvidia_init(void)
92{
93 uint32_t reg32;
94
95 get_io_perms();
96
Carl-Daniel Hailfinger40446ee2011-03-07 01:08:09 +000097 io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia);
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +000098
Uwe Hermann2bc98f62009-09-30 18:29:55 +000099 io_base_addr += 0x300000;
Sean Nelson8e5e73e2010-01-09 23:54:05 +0000100 msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000101
David Hendricks8bb20212011-06-14 01:35:36 +0000102 nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE);
103
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000104 /* Must be done before rpci calls. */
David Hendricks8bb20212011-06-14 01:35:36 +0000105 if (register_shutdown(gfxnvidia_shutdown, NULL))
106 return 1;
107
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000108 /* Allow access to flash interface (will disable screen). */
109 reg32 = pci_read_long(pcidev_dev, 0x50);
110 reg32 &= ~(1 << 0);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000111 rpci_write_long(pcidev_dev, 0x50, reg32);
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000112
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000113 /* Write/erase doesn't work. */
114 programmer_may_write = 0;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000115 register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL);
Carl-Daniel Hailfingerbf3af292010-07-29 14:41:46 +0000116
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000117 return 0;
118}
119
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000120static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
121 chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000122{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000123 pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000124}
125
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000126static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
127 const chipaddr addr)
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000128{
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +0000129 return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
Uwe Hermann2bc98f62009-09-30 18:29:55 +0000130}