blob: 727a31ba8c5aa2dd19d9703765f0724cf5fcb3bc [file] [log] [blame]
Stefan Tauner1e146392011-09-15 23:52:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de>
5 * Copyright (c) 2011 Stefan Tauner
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Stefan Tauner1e146392011-09-15 23:52:55 +000016 */
17
Stefan Tauner1e146392011-09-15 23:52:55 +000018#ifndef __ICH_DESCRIPTORS_H__
19#define __ICH_DESCRIPTORS_H__ 1
20
Nico Huber4d440a72017-08-15 11:26:48 +020021#include <sys/types.h>
Stefan Tauner1e146392011-09-15 23:52:55 +000022#include <stdint.h>
Stefan Taunera8d838d2011-11-06 23:51:09 +000023#include "programmer.h" /* for enum ich_chipset */
Stefan Tauner1e146392011-09-15 23:52:55 +000024
25/* FIXME: Replace with generic return codes */
26#define ICH_RET_OK 0
27#define ICH_RET_ERR -1
28#define ICH_RET_WARN -2
29#define ICH_RET_PARAM -3
30#define ICH_RET_OOB -4
31
32#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */
Nico Huberd54e4f42017-03-23 23:45:47 +010033#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000034 /* 0-1: reserved */
35#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */
36#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF)
37#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */
38#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF)
39 /* 15-31: reserved */
40
41#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */
Nico Huberd54e4f42017-03-23 23:45:47 +010042#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */
Stefan Tauner1e146392011-09-15 23:52:55 +000043
44/* Field locations and semantics for LVSCC, UVSCC and related words in the flash
45 * descriptor are equal therefore they all share the same macros below. */
46#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */
47#define VSCC_BES (0x3 << VSCC_BES_OFF)
48#define VSCC_WG_OFF 2 /* 2: Write Granularity */
49#define VSCC_WG (0x1 << VSCC_WG_OFF)
50#define VSCC_WSR_OFF 3 /* 3: Write Status Required */
51#define VSCC_WSR (0x1 << VSCC_WSR_OFF)
52#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */
53#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF)
54 /* 5-7: reserved */
55#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */
56#define VSCC_EO (0xff << VSCC_EO_OFF)
57 /* 16-22: reserved */
58#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */
59#define VSCC_VCL (0x1 << VSCC_VCL_OFF)
60 /* 24-31: reserved */
61
Nico Huberfa622942017-03-24 17:25:37 +010062#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x07fff000)
63#define ICH_FREG_LIMIT(flreg) ((((flreg) >> 4) & 0x07fff000) | 0x00000fff)
Stefan Tauner1e146392011-09-15 23:52:55 +000064
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +000065void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity, bool print_vcl);
Stefan Tauner1e146392011-09-15 23:52:55 +000066
67struct ich_desc_content {
68 uint32_t FLVALSIG; /* 0x00 */
69 union { /* 0x04 */
70 uint32_t FLMAP0;
71 struct {
72 uint32_t FCBA :8, /* Flash Component Base Address */
73 NC :2, /* Number Of Components */
74 :6,
75 FRBA :8, /* Flash Region Base Address */
Nico Huberfa622942017-03-24 17:25:37 +010076 NR :3, /* Number Of Regions (reserved from Skylake on) */
Stefan Tauner1e146392011-09-15 23:52:55 +000077 :5;
78 };
79 };
80 union { /* 0x08 */
81 uint32_t FLMAP1;
82 struct {
83 uint32_t FMBA :8, /* Flash Master Base Address */
84 NM :3, /* Number Of Masters */
85 :5,
86 FISBA :8, /* Flash ICH Strap Base Address */
87 ISL :8; /* ICH Strap Length */
88 };
89 };
90 union { /* 0x0c */
91 uint32_t FLMAP2;
92 struct {
Nico Huber1dc3d422017-06-17 00:09:31 +020093 uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */
94 MSL :8, /* MCH Strap Length */
95 ICCRIBA :8, /* ICC Reg. Init Base Addr. (new since Sandy Bridge) */
96 RIL :8; /* Register Init Length (new since Hawell) */
Stefan Tauner1e146392011-09-15 23:52:55 +000097 };
98 };
99};
100
101struct ich_desc_component {
102 union { /* 0x00 */
103 uint32_t FLCOMP; /* Flash Components Register */
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000104 /* FLCOMP encoding on various generations:
105 *
106 * Chipset/Generation max_speed dual_output density
Elyes HAOUASac01baa2018-05-28 16:52:21 +0200107 * [MHz] bits max. bits
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000108 * ICH8: 33 N/A 5 0:2, 3:5
109 * ICH9: 33 N/A 5 0:2, 3:5
110 * ICH10: 33 N/A 5 0:2, 3:5
111 * Ibex Peak/5: 50 N/A 5 0:2, 3:5
112 * Cougar Point/6: 50 30 5 0:2, 3:5
113 * Patsburg: 50 30 5 0:2, 3:5
114 * Panther Point/7 50 30 5 0:2, 3:5
115 * Lynx Point/8: 50 30 7 0:3, 4:7
Nico Huberfa622942017-03-24 17:25:37 +0100116 * Wildcat Point/9: 50 30 (multi I/O) 7 0:3, 4:7
117 * Sunrise Point/100: 48 30 7 0:3, 4:7
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000118 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000119 struct {
Duncan Laurie823096e2014-08-20 15:39:38 +0000120 uint32_t :17,
Stefan Tauner1e146392011-09-15 23:52:55 +0000121 freq_read :3,
122 fastread :1,
123 freq_fastread :3,
124 freq_write :3,
125 freq_read_id :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000126 dual_output :1, /* new since Cougar Point/6 */
127 :1;
128 } modes;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000129 struct {
130 uint32_t comp1_density :3,
131 comp2_density :3,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000132 :26;
133 } dens_old;
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000134 struct {
135 uint32_t comp1_density :4, /* new since Lynx Point/8 */
136 comp2_density :4,
Tai-Hong Wu60dead42015-01-05 23:00:14 +0000137 :24;
138 } dens_new;
Stefan Tauner1e146392011-09-15 23:52:55 +0000139 };
140 union { /* 0x04 */
141 uint32_t FLILL; /* Flash Invalid Instructions Register */
142 struct {
143 uint32_t invalid_instr0 :8,
144 invalid_instr1 :8,
145 invalid_instr2 :8,
146 invalid_instr3 :8;
147 };
148 };
149 union { /* 0x08 */
Nico Huberfa622942017-03-24 17:25:37 +0100150 uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000151 struct {
152 uint32_t FPBA :13, /* Flash Partition Boundary Addr */
153 :19;
154 };
Nico Huberfa622942017-03-24 17:25:37 +0100155 uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */
Stefan Tauner1e146392011-09-15 23:52:55 +0000156 struct {
Nico Huberfa622942017-03-24 17:25:37 +0100157 uint32_t invalid_instr4 :8,
158 invalid_instr5 :8,
159 invalid_instr6 :8,
160 invalid_instr7 :8;
Stefan Tauner1e146392011-09-15 23:52:55 +0000161 };
162 };
163};
164
David Hendricks8e762302017-08-09 22:21:31 -0700165#define MAX_NUM_FLREGS 16
Nico Huberfa622942017-03-24 17:25:37 +0100166struct ich_desc_region {
167 /*
168 * Number of entries and width differ on various generations:
169 *
170 * Chipset/Generation #FLREGs width (bits)
171 * ICH8 .. Panther Point/7 5 13
172 * Lynx Point/8 .. Wildcat Point/9 7 15
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200173 * Sunrise Point/100 .. 200 Series 10 15
David Hendricks8e762302017-08-09 22:21:31 -0700174 * Lewisburg/100 .. 16 15
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200175 * Cannon Point/300 .. 16 15
Nico Huberfa622942017-03-24 17:25:37 +0100176 */
177 union {
178 uint32_t FLREGs[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */
179
180 /* only used for bit-field check */
181 struct {
182 uint32_t base :13,
183 :3,
184 limit :13,
185 :3;
186 } old_reg[MAX_NUM_FLREGS];
187 };
188};
189
David Hendricks8e762302017-08-09 22:21:31 -0700190#define MAX_NUM_MASTERS 6 /* 5 prior to C620/Lewisburg PCH */
Stefan Tauner1e146392011-09-15 23:52:55 +0000191struct ich_desc_master {
192 union {
Nico Huberfa622942017-03-24 17:25:37 +0100193 uint32_t FLMSTRs[MAX_NUM_MASTERS]; /* Flash Masters */
194 /* For pre-Skylake platforms */
Stefan Tauner1e146392011-09-15 23:52:55 +0000195 struct {
196 uint32_t BIOS_req_ID :16,
197 BIOS_descr_r :1,
198 BIOS_BIOS_r :1,
199 BIOS_ME_r :1,
200 BIOS_GbE_r :1,
201 BIOS_plat_r :1,
202 :3,
203 BIOS_descr_w :1,
204 BIOS_BIOS_w :1,
205 BIOS_ME_w :1,
206 BIOS_GbE_w :1,
207 BIOS_plat_w :1,
208 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000209 uint32_t ME_req_ID :16,
210 ME_descr_r :1,
211 ME_BIOS_r :1,
212 ME_ME_r :1,
213 ME_GbE_r :1,
214 ME_plat_r :1,
215 :3,
216 ME_descr_w :1,
217 ME_BIOS_w :1,
218 ME_ME_w :1,
219 ME_GbE_w :1,
220 ME_plat_w :1,
221 :3;
Stefan Tauner1e146392011-09-15 23:52:55 +0000222 uint32_t GbE_req_ID :16,
223 GbE_descr_r :1,
224 GbE_BIOS_r :1,
225 GbE_ME_r :1,
226 GbE_GbE_r :1,
227 GbE_plat_r :1,
228 :3,
229 GbE_descr_w :1,
230 GbE_BIOS_w :1,
231 GbE_ME_w :1,
232 GbE_GbE_w :1,
233 GbE_plat_w :1,
234 :3;
235 };
Nico Huberfa622942017-03-24 17:25:37 +0100236 /* From Skylake on */
237 struct {
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200238 uint32_t ext_read :4,
239 ext_write :4,
240 read :12,
241 write :12;
Nico Huberfa622942017-03-24 17:25:37 +0100242 } mstr[MAX_NUM_MASTERS];
Stefan Tauner1e146392011-09-15 23:52:55 +0000243 };
244};
245
Stefan Taunerb3850962011-12-24 00:00:32 +0000246struct ich_desc_north_strap {
247 union {
248 uint32_t STRPs[1]; /* current maximum: ich8 */
249 struct { /* ich8 */
250 struct { /* STRP2 (in the datasheet) */
251 uint32_t MDB :1,
252 :31;
253 };
254 } ich8;
255 };
256};
257
258struct ich_desc_south_strap {
259 union {
Angel Pons11a35982020-07-10 17:04:10 +0200260 uint32_t STRPs[23]; /* current maximum: gemini lake */
Stefan Taunerb3850962011-12-24 00:00:32 +0000261 struct { /* ich8 */
262 struct { /* STRP1 */
263 uint32_t ME_DISABLE :1,
264 :6,
265 TCOMODE :1,
266 ASD :7,
267 BMCMODE :1,
268 :3,
269 GLAN_PCIE_SEL :1,
270 GPIO12_SEL :2,
271 SPICS1_LANPHYPC_SEL :1,
272 MESM2SEL :1,
273 :1,
274 ASD2 :7;
275 };
276 } ich8;
277 struct { /* ibex peak */
278 struct { /* STRP0 */
279 uint32_t :1,
280 cs_ss2 :1,
281 :5,
282 SMB_EN :1,
283 SML0_EN :1,
284 SML1_EN :1,
285 SML1FRQ :2,
286 SMB0FRQ :2,
287 SML0FRQ :2,
288 :4,
289 LANPHYPC_GP12_SEL :1,
290 cs_ss1 :1,
291 :2,
292 DMI_REQID_DIS :1,
293 :4,
294 BBBS :2,
295 :1;
296 };
297 struct { /* STRP1 */
298 uint32_t cs_ss3 :4,
299 :28;
300 };
301 struct { /* STRP2 */
302 uint32_t :8,
303 MESMASDEN :1,
304 MESMASDA :7,
305 :8,
306 MESMI2CEN :1,
307 MESMI2CA :7;
308 };
309 struct { /* STRP3 */
310 uint32_t :32;
311 };
312 struct { /* STRP4 */
313 uint32_t PHYCON :2,
314 :6,
315 GBEMAC_SMBUS_ADDR_EN :1,
316 GBEMAC_SMBUS_ADDR :7,
317 :1,
318 GBEPHY_SMBUS_ADDR :7,
319 :8;
320 };
321 struct { /* STRP5 */
322 uint32_t :32;
323 };
324 struct { /* STRP6 */
325 uint32_t :32;
326 };
327 struct { /* STRP7 */
328 uint32_t MESMA2UDID_VENDOR :16,
329 MESMA2UDID_DEVICE :16;
330 };
331 struct { /* STRP8 */
332 uint32_t :32;
333 };
334 struct { /* STRP9 */
335 uint32_t PCIEPCS1 :2,
336 PCIEPCS2 :2,
337 PCIELR1 :1,
338 PCIELR2 :1,
339 DMILR :1,
340 :1,
341 PHY_PCIEPORTSEL :3,
342 PHY_PCIE_EN :1,
343 :20;
344 };
345 struct { /* STRP10 */
346 uint32_t :1,
347 ME_BOOT_FLASH :1,
348 cs_ss5 :1,
349 VE_EN :1,
350 :4,
351 MMDDE :1,
352 MMADDR :7,
353 cs_ss7 :1,
354 :1,
355 ICC_SEL :3,
356 MER_CL1 :1,
357 :10;
358 };
359 struct { /* STRP11 */
360 uint32_t SML1GPAEN :1,
361 SML1GPA :7,
362 :16,
363 SML1I2CAEN :1,
364 SML1I2CA :7;
365 };
366 struct { /* STRP12 */
367 uint32_t :32;
368 };
369 struct { /* STRP13 */
370 uint32_t :32;
371 };
372 struct { /* STRP14 */
373 uint32_t :8,
374 VE_EN2 :1,
375 :5,
376 VE_BOOT_FLASH :1,
377 :1,
378 BW_SSD :1,
379 NVMHCI_EN :1,
380 :14;
381 };
382 struct { /* STRP15 */
383 uint32_t :3,
384 cs_ss6 :2,
385 :1,
386 IWL_EN :1,
387 :1,
388 t209min :2,
389 :22;
390 };
391 } ibex;
392 struct { /* cougar point */
393 struct { /* STRP0 */
394 uint32_t :1,
395 cs_ss1 :1,
396 :5,
397 SMB_EN :1,
398 SML0_EN :1,
399 SML1_EN :1,
400 SML1FRQ :2,
401 SMB0FRQ :2,
402 SML0FRQ :2,
403 :4,
404 LANPHYPC_GP12_SEL :1,
405 LINKSEC_DIS :1,
406 :2,
407 DMI_REQID_DIS :1,
408 :4,
409 BBBS :2,
410 :1;
411 };
412 struct { /* STRP1 */
413 uint32_t cs_ss3 :4,
414 :4,
415 cs_ss2 :1,
416 :28;
417 };
418 struct { /* STRP2 */
419 uint32_t :8,
420 MESMASDEN :1,
421 MESMASDA :7,
422 MESMMCTPAEN :1,
423 MESMMCTPA :7,
424 MESMI2CEN :1,
425 MESMI2CA :7;
426 };
427 struct { /* STRP3 */
428 uint32_t :32;
429 };
430 struct { /* STRP4 */
431 uint32_t PHYCON :2,
432 :6,
433 GBEMAC_SMBUS_ADDR_EN :1,
434 GBEMAC_SMBUS_ADDR :7,
435 :1,
436 GBEPHY_SMBUS_ADDR :7,
437 :8;
438 };
439 struct { /* STRP5 */
440 uint32_t :32;
441 };
442 struct { /* STRP6 */
443 uint32_t :32;
444 };
445 struct { /* STRP7 */
446 uint32_t MESMA2UDID_VENDOR :16,
447 MESMA2UDID_DEVICE :16;
448 };
449 struct { /* STRP8 */
450 uint32_t :32;
451 };
452 struct { /* STRP9 */
453 uint32_t PCIEPCS1 :2,
454 PCIEPCS2 :2,
455 PCIELR1 :1,
456 PCIELR2 :1,
457 DMILR :1,
458 cs_ss4 :1,
459 PHY_PCIEPORTSEL :3,
460 PHY_PCIE_EN :1,
461 :2,
462 SUB_DECODE_EN :1,
463 :7,
464 PCHHOT_SML1ALERT_SEL :1,
465 :9;
466 };
467 struct { /* STRP10 */
468 uint32_t :1,
469 ME_BOOT_FLASH :1,
470 :6,
471 MDSMBE_EN :1,
472 MDSMBE_ADD :7,
473 :2,
474 ICC_SEL :3,
475 MER_CL1 :1,
476 ICC_PRO_SEL :1,
477 Deep_SX_EN :1,
478 ME_DBG_LAN :1,
479 :7;
480 };
481 struct { /* STRP11 */
482 uint32_t SML1GPAEN :1,
483 SML1GPA :7,
484 :16,
485 SML1I2CAEN :1,
486 SML1I2CA :7;
487 };
488 struct { /* STRP12 */
489 uint32_t :32;
490 };
491 struct { /* STRP13 */
492 uint32_t :32;
493 };
494 struct { /* STRP14 */
495 uint32_t :32;
496 };
497 struct { /* STRP15 */
498 uint32_t cs_ss6 :6,
499 IWL_EN :1,
500 cs_ss5 :2,
501 :4,
502 SMLINK1_THERM_SEL :1,
503 SLP_LAN_GP29_SEL :1,
504 :16;
505 };
506 struct { /* STRP16 */
507 uint32_t :32;
508 };
509 struct { /* STRP17 */
510 uint32_t ICML :1,
511 cs_ss7 :1,
512 :30;
513 };
514 } cougar;
515 };
516};
517
518struct ich_desc_upper_map {
519 union {
520 uint32_t FLUMAP1; /* Flash Upper Map 1 */
521 struct {
522 uint32_t VTBA :8, /* ME VSCC Table Base Address */
523 VTL :8, /* ME VSCC Table Length */
524 :16;
525 };
526 };
527 struct {
528 union { /* JEDEC-ID Register */
529 uint32_t JID;
530 struct {
531 uint32_t vid :8, /* Vendor ID */
532 cid0 :8, /* Component ID 0 */
533 cid1 :8, /* Component ID 1 */
534 :8;
535 };
536 };
537 union { /* Vendor Specific Component Capabilities */
538 uint32_t VSCC;
539 struct {
540 uint32_t ubes :2, /* Upper Block/Sector Erase Size */
541 uwg :1, /* Upper Write Granularity */
542 uwsr :1, /* Upper Write Status Required */
543 uwews :1, /* Upper Write Enable on Write Status */
544 :3,
545 ueo :8, /* Upper Erase Opcode */
546 lbes :2, /* Lower Block/Sector Erase Size */
547 lwg :1, /* Lower Write Granularity */
548 lwsr :1, /* Lower Write Status Required */
549 lwews :1, /* Lower Write Enable on Write Status */
550 :3,
551 leo :16; /* Lower Erase Opcode */
552 };
553 };
554 } vscc_table[128];
555};
Stefan Taunerb3850962011-12-24 00:00:32 +0000556
Stefan Tauner1e146392011-09-15 23:52:55 +0000557struct ich_descriptors {
558 struct ich_desc_content content;
559 struct ich_desc_component component;
560 struct ich_desc_region region;
561 struct ich_desc_master master;
Stefan Taunerb3850962011-12-24 00:00:32 +0000562 struct ich_desc_north_strap north;
563 struct ich_desc_south_strap south;
564 struct ich_desc_upper_map upper;
Stefan Tauner1e146392011-09-15 23:52:55 +0000565};
566
David Hendricks0eb00d42017-09-01 20:02:36 -0700567struct ich_layout {
568 struct flashrom_layout base;
David Hendricks7a8305f2017-09-01 20:16:58 -0700569 struct romentry entries[MAX_NUM_FLREGS];
David Hendricks0eb00d42017-09-01 20:02:36 -0700570};
571
Nico Huberfa622942017-03-24 17:25:37 +0100572ssize_t ich_number_of_regions(enum ich_chipset cs, const struct ich_desc_content *content);
573ssize_t ich_number_of_masters(enum ich_chipset cs, const struct ich_desc_content *content);
574
Nico Huber67d71792017-06-17 03:10:15 +0200575void prettyprint_ich_chipset(enum ich_chipset cs);
Stefan Taunerb3850962011-12-24 00:00:32 +0000576void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000577
Nico Huberfa622942017-03-24 17:25:37 +0100578void prettyprint_ich_descriptor_content(enum ich_chipset cs, const struct ich_desc_content *content);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000579void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100580void prettyprint_ich_descriptor_region(enum ich_chipset cs, const struct ich_descriptors *desc);
581void prettyprint_ich_descriptor_master(enum ich_chipset cs, const struct ich_descriptors *desc);
Stefan Tauner1e146392011-09-15 23:52:55 +0000582
Stefan Taunerb3850962011-12-24 00:00:32 +0000583void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap);
584void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc);
Nico Huberfa622942017-03-24 17:25:37 +0100585int read_ich_descriptors_from_dump(const uint32_t *dump, size_t len, enum ich_chipset *cs, struct ich_descriptors *desc);
Stefan Taunerb3850962011-12-24 00:00:32 +0000586
Nico Huberd54e4f42017-03-23 23:45:47 +0100587int read_ich_descriptors_via_fdo(enum ich_chipset cs, void *spibar, struct ich_descriptors *desc);
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +0000588int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors *desc, uint8_t idx);
Stefan Tauner1e146392011-09-15 23:52:55 +0000589
Nico Huber305f4172013-06-14 11:55:26 +0200590int layout_from_ich_descriptors(struct ich_layout *, const void *dump, size_t len);
591
Stefan Tauner1e146392011-09-15 23:52:55 +0000592#endif /* __ICH_DESCRIPTORS_H__ */