blob: 9d1a9ada9927fc77faacafec785e8ab72072cc07 [file] [log] [blame]
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2009 coresystems GmbH
7 * Copyright (C) 2006-2009 Carl-Daniel Hailfinger
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000018 */
19
20#ifndef __PROGRAMMER_H__
21#define __PROGRAMMER_H__ 1
22
Nico Huber1cf407b2017-11-10 20:18:23 +010023#include <stdint.h>
24
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000025#include "flash.h" /* for chipaddr and flashctx */
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +000026
Stefan Tauneraf358d62012-12-27 18:40:26 +000027enum programmer_type {
28 PCI = 1, /* to detect uninitialized values */
29 USB,
30 OTHER,
31};
32
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000033struct dev_entry {
34 uint16_t vendor_id;
35 uint16_t device_id;
36 const enum test_state status;
37 const char *vendor_name;
38 const char *device_name;
39};
40
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000041struct programmer_entry {
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000042 const char *name;
Stefan Tauneraf358d62012-12-27 18:40:26 +000043 const enum programmer_type type;
44 union {
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000045 const struct dev_entry *const dev;
Stefan Tauneraf358d62012-12-27 18:40:26 +000046 const char *const note;
47 } devs;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000048
49 int (*init) (void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000050
Stefan Tauner305e0b92013-07-17 23:46:44 +000051 void *(*map_flash_region) (const char *descr, uintptr_t phys_addr, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000052 void (*unmap_flash_region) (void *virt_addr, size_t len);
53
Stefan Taunerf80419c2014-05-02 15:41:42 +000054 void (*delay) (unsigned int usecs);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000055};
56
Thomas Heijligendee884e2021-03-31 19:09:44 +020057extern const struct programmer_entry *const programmer_table[];
Thomas Heijligen113f3bc2021-05-19 13:53:34 +020058extern const size_t programmer_table_size;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000059
Thomas Heijligen508fb162021-06-10 15:17:53 +020060/* programmer drivers */
61extern const struct programmer_entry programmer_internal;
62extern const struct programmer_entry programmer_dummy;
63extern const struct programmer_entry programmer_nic3com;
64extern const struct programmer_entry programmer_gfxnvidia;
65extern const struct programmer_entry programmer_raiden_debug_spi;
66extern const struct programmer_entry programmer_drkaiser;
67extern const struct programmer_entry programmer_nicrealtek;
68extern const struct programmer_entry programmer_nicnatsemi;
69extern const struct programmer_entry programmer_nicintel;
70extern const struct programmer_entry programmer_nicintel_spi;
71extern const struct programmer_entry programmer_nicintel_eeprom;
72extern const struct programmer_entry programmer_ogp_spi;
73extern const struct programmer_entry programmer_satamv;
74extern const struct programmer_entry programmer_satasii;
75extern const struct programmer_entry programmer_atahpt;
76extern const struct programmer_entry programmer_atavia;
77extern const struct programmer_entry programmer_atapromise;
78extern const struct programmer_entry programmer_it8212;
79extern const struct programmer_entry programmer_ft2232_spi;
80extern const struct programmer_entry programmer_usbblaster_spi;
81extern const struct programmer_entry programmer_mstarddc_spi;
82extern const struct programmer_entry programmer_pickit2_spi;
83extern const struct programmer_entry programmer_stlinkv3_spi;
84extern const struct programmer_entry programmer_rayer_spi;
85extern const struct programmer_entry programmer_pony_spi;
86extern const struct programmer_entry programmer_buspirate_spi;
87extern const struct programmer_entry programmer_linux_mtd;
88extern const struct programmer_entry programmer_linux_spi;
89extern const struct programmer_entry programmer_dediprog;
90extern const struct programmer_entry programmer_developerbox;
91extern const struct programmer_entry programmer_ch341a_spi;
92extern const struct programmer_entry programmer_digilent_spi;
93extern const struct programmer_entry programmer_ene_lpc;
94extern const struct programmer_entry programmer_jlink_spi;
95extern const struct programmer_entry programmer_ni845x_spi;
96extern const struct programmer_entry programmer_mec1308;
97extern const struct programmer_entry programmer_serprog;
98extern const struct programmer_entry programmer_lspcon_i2c_spi;
99extern const struct programmer_entry programmer_realtek_mst_i2c_spi;
100
Thomas Heijligen5d25f042021-06-01 14:37:12 +0200101int programmer_init(const struct programmer_entry *prog, const char *param);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000102int programmer_shutdown(void);
103
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000104struct bitbang_spi_master {
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000105 /* Note that CS# is active low, so val=0 means the chip is active. */
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000106 void (*set_cs) (int val, void *spi_data);
107 void (*set_sck) (int val, void *spi_data);
108 void (*set_mosi) (int val, void *spi_data);
109 int (*get_miso) (void *spi_data);
110 void (*request_bus) (void *spi_data);
111 void (*release_bus) (void *spi_data);
Daniel Thompsonb623f402018-06-05 09:38:19 +0100112 /* optional functions to optimize xfers */
Anastasia Klimchuk5f5eaeb2021-05-26 09:54:08 +1000113 void (*set_sck_set_mosi) (int sck, int mosi, void *spi_data);
114 int (*set_sck_get_miso) (int sck, void *spi_data);
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000115 /* Length of half a clock period in usecs. */
116 unsigned int half_period;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000117};
118
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000119#if NEED_PCI == 1
Patrick Georgi32508eb2012-07-20 20:35:14 +0000120struct pci_dev;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000121
122/* pcidev.c */
Stefan Tauner0ccec8f2014-06-01 23:49:03 +0000123// FIXME: This needs to be local, not global(?)
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000124extern struct pci_access *pacc;
125int pci_init_common(void);
126uintptr_t pcidev_readbar(struct pci_dev *dev, int bar);
127struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar);
128/* rpci_write_* are reversible writes. The original PCI config space register
129 * contents will be restored on shutdown.
Youness Alaouia54ceb12017-07-26 18:03:36 -0400130 * To clone the pci_dev instances internally, the `pacc` global
131 * variable has to reference a pci_access method that is compatible
132 * with the given pci_dev handle. The referenced pci_access (not
133 * the variable) has to stay valid until the shutdown handlers are
134 * finished.
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000135 */
136int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data);
137int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data);
138int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data);
139#endif
140
141#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000142struct penable {
143 uint16_t vendor_id;
144 uint16_t device_id;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200145 enum chipbustype buses;
Stefan Tauner2c20b282012-07-28 19:35:26 +0000146 const enum test_state status;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000147 const char *vendor_name;
148 const char *device_name;
149 int (*doit) (struct pci_dev *dev, const char *name);
150};
151
152extern const struct penable chipset_enables[];
153
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000154enum board_match_phase {
155 P1,
156 P2,
157 P3
158};
159
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000160struct board_match {
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000161 /* Any device, but make it sensible, like the ISA bridge. */
162 uint16_t first_vendor;
163 uint16_t first_device;
164 uint16_t first_card_vendor;
165 uint16_t first_card_device;
166
167 /* Any device, but make it sensible, like
168 * the host bridge. May be NULL.
169 */
170 uint16_t second_vendor;
171 uint16_t second_device;
172 uint16_t second_card_vendor;
173 uint16_t second_card_device;
174
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000175 /* Pattern to match DMI entries. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000176 const char *dmi_pattern;
177
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000178 /* The vendor / part name from the coreboot table. May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000179 const char *lb_vendor;
180 const char *lb_part;
181
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000182 enum board_match_phase phase;
183
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000184 const char *vendor_name;
185 const char *board_name;
186
187 int max_rom_decode_parallel;
Stefan Tauner2c20b282012-07-28 19:35:26 +0000188 const enum test_state status;
Stefan Tauner7bcacb12011-05-26 01:35:19 +0000189 int (*enable) (void); /* May be NULL. */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000190};
191
Carl-Daniel Hailfinger97d5b122011-08-31 16:19:50 +0000192extern const struct board_match board_matches[];
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000193
194struct board_info {
195 const char *vendor;
196 const char *name;
Stefan Tauner2c20b282012-07-28 19:35:26 +0000197 const enum test_state working;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000198#ifdef CONFIG_PRINT_WIKI
199 const char *url;
200 const char *note;
201#endif
202};
203
204extern const struct board_info boards_known[];
205extern const struct board_info laptops_known[];
206#endif
207
208/* udelay.c */
Stefan Taunerf80419c2014-05-02 15:41:42 +0000209void myusec_delay(unsigned int usecs);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000210void myusec_calibrate_delay(void);
Stefan Taunerf80419c2014-05-02 15:41:42 +0000211void internal_sleep(unsigned int usecs);
212void internal_delay(unsigned int usecs);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000213
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000214#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000215/* board_enable.c */
Stefan Tauner600576b2014-06-12 22:57:36 +0000216int selfcheck_board_enables(void);
Jacob Garber1c091d12019-08-12 11:14:14 -0600217int board_parse_parameter(const char *boardstring, char **vendor, char **model);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000218void w836xx_ext_enter(uint16_t port);
219void w836xx_ext_leave(uint16_t port);
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000220void probe_superio_winbond(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000221int it8705f_write_enable(uint8_t port);
222uint8_t sio_read(uint16_t port, uint8_t reg);
223void sio_write(uint16_t port, uint8_t reg, uint8_t data);
224void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000225void board_handle_before_superio(void);
226void board_handle_before_laptop(void);
Stefan Taunerfa9fa712012-09-24 21:29:29 +0000227int board_flash_enable(const char *vendor, const char *model, const char *cb_vendor, const char *cb_model);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000228
229/* chipset_enable.c */
230int chipset_flash_enable(void);
231
232/* processor_enable.c */
233int processor_flash_enable(void);
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000234#endif
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000235
236/* physmap.c */
Stefan Tauner305e0b92013-07-17 23:46:44 +0000237void *physmap(const char *descr, uintptr_t phys_addr, size_t len);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000238void *rphysmap(const char *descr, uintptr_t phys_addr, size_t len);
Niklas Söderlund5d307202013-09-14 09:02:27 +0000239void *physmap_ro(const char *descr, uintptr_t phys_addr, size_t len);
Carl-Daniel Hailfinger43eac032014-03-05 00:16:16 +0000240void *physmap_ro_unaligned(const char *descr, uintptr_t phys_addr, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000241void physunmap(void *virt_addr, size_t len);
Carl-Daniel Hailfinger43eac032014-03-05 00:16:16 +0000242void physunmap_unaligned(void *virt_addr, size_t len);
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000243#if CONFIG_INTERNAL == 1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000244int setup_cpu_msr(int cpu);
245void cleanup_cpu_msr(void);
246
247/* cbtable.c */
Stefan Taunerb4e06bd2012-08-20 00:24:22 +0000248int cb_parse_table(const char **vendor, const char **model);
Nico Huber519be662018-12-23 20:03:35 +0100249int cb_check_image(const uint8_t *bios, unsigned int size);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000250
251/* dmi.c */
Sean Nelson4c6d3a42013-09-11 23:35:03 +0000252#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000253extern int has_dmi_support;
254void dmi_init(void);
255int dmi_match(const char *pattern);
Sean Nelson4c6d3a42013-09-11 23:35:03 +0000256#endif // defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000257
258/* internal.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000259struct superio {
260 uint16_t vendor;
261 uint16_t port;
262 uint16_t model;
263};
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000264extern struct superio superios[];
265extern int superio_count;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000266#define SUPERIO_VENDOR_NONE 0x0
267#define SUPERIO_VENDOR_ITE 0x1
Carl-Daniel Hailfingerf5e62cb2012-05-06 22:48:01 +0000268#define SUPERIO_VENDOR_WINBOND 0x2
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000269#endif
270#if NEED_PCI == 1
Uwe Hermann24c35e42011-07-13 11:22:03 +0000271struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t devclass);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000272struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
273struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
274 uint16_t card_vendor, uint16_t card_device);
275#endif
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000276int rget_io_perms(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000277#if CONFIG_INTERNAL == 1
278extern int is_laptop;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +0000279extern int laptop_ok;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000280extern int force_boardenable;
281extern int force_boardmismatch;
282void probe_superio(void);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000283int register_superio(struct superio s);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000284extern enum chipbustype internal_buses_supported;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000285#endif
286
287/* hwaccess.c */
288void mmio_writeb(uint8_t val, void *addr);
289void mmio_writew(uint16_t val, void *addr);
290void mmio_writel(uint32_t val, void *addr);
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100291uint8_t mmio_readb(const void *addr);
292uint16_t mmio_readw(const void *addr);
293uint32_t mmio_readl(const void *addr);
294void mmio_readn(const void *addr, uint8_t *buf, size_t len);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000295void mmio_le_writeb(uint8_t val, void *addr);
296void mmio_le_writew(uint16_t val, void *addr);
297void mmio_le_writel(uint32_t val, void *addr);
Nico Huberb4d8a2a2017-03-17 17:19:15 +0100298uint8_t mmio_le_readb(const void *addr);
299uint16_t mmio_le_readw(const void *addr);
300uint32_t mmio_le_readl(const void *addr);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000301#define pci_mmio_writeb mmio_le_writeb
302#define pci_mmio_writew mmio_le_writew
303#define pci_mmio_writel mmio_le_writel
304#define pci_mmio_readb mmio_le_readb
305#define pci_mmio_readw mmio_le_readw
306#define pci_mmio_readl mmio_le_readl
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000307void rmmio_writeb(uint8_t val, void *addr);
308void rmmio_writew(uint16_t val, void *addr);
309void rmmio_writel(uint32_t val, void *addr);
310void rmmio_le_writeb(uint8_t val, void *addr);
311void rmmio_le_writew(uint16_t val, void *addr);
312void rmmio_le_writel(uint32_t val, void *addr);
313#define pci_rmmio_writeb rmmio_le_writeb
314#define pci_rmmio_writew rmmio_le_writew
315#define pci_rmmio_writel rmmio_le_writel
316void rmmio_valb(void *addr);
317void rmmio_valw(void *addr);
318void rmmio_vall(void *addr);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000319
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000320/* bitbang_spi.c */
Anastasia Klimchuk30815fc2021-05-31 11:20:01 +1000321int register_spi_bitbang_master(const struct bitbang_spi_master *master, void *spi_data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000322
Miklós Márton2d20d6d2018-01-30 20:20:15 +0100323
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000324/* flashrom.c */
325struct decode_sizes {
326 uint32_t parallel;
327 uint32_t lpc;
328 uint32_t fwh;
329 uint32_t spi;
330};
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000331// FIXME: These need to be local, not global
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000332extern struct decode_sizes max_rom_decode;
333extern int programmer_may_write;
334extern unsigned long flashbase;
Stefan Tauner9e3a6982014-08-15 17:17:59 +0000335unsigned int count_max_decode_exceedings(const struct flashctx *flash);
Stefan Tauner66652442011-06-26 17:38:17 +0000336char *extract_programmer_param(const char *param_name);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000337
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000338/* spi.c */
Michael Karcher62797512011-05-11 17:07:02 +0000339#define MAX_DATA_UNSPECIFIED 0
340#define MAX_DATA_READ_UNLIMITED 64 * 1024
341#define MAX_DATA_WRITE_UNLIMITED 256
Nico Huber1cf407b2017-11-10 20:18:23 +0100342
343#define SPI_MASTER_4BA (1U << 0) /**< Can handle 4-byte addresses */
Nico Huberdc5af542018-12-22 16:54:59 +0100344#define SPI_MASTER_NO_4BA_MODES (1U << 1) /**< Compatibility modes (i.e. extended address
345 register, 4BA mode switch) don't work */
Nico Huber1cf407b2017-11-10 20:18:23 +0100346
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000347struct spi_master {
Nico Huber1cf407b2017-11-10 20:18:23 +0100348 uint32_t features;
Stefan Tauner23e10b82016-01-23 16:16:49 +0000349 unsigned int max_data_read; // (Ideally,) maximum data read size in one go (excluding opcode+address).
350 unsigned int max_data_write; // (Ideally,) maximum data write size in one go (excluding opcode+address).
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000351 int (*command)(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000352 const unsigned char *writearr, unsigned char *readarr);
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000353 int (*multicommand)(const struct flashctx *flash, struct spi_command *cmds);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000354
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000355 /* Optimized functions for this master */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000356 int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000357 int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
358 int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
Edward O'Callaghanec942502021-01-06 14:10:52 +1100359 void *data;
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000360};
361
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000362int default_spi_send_command(const struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000363 const unsigned char *writearr, unsigned char *readarr);
Edward O'Callaghane4ddc362020-04-12 17:27:53 +1000364int default_spi_send_multicommand(const struct flashctx *flash, struct spi_command *cmds);
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000365int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000366int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
367int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
Nico Huber7e496852021-05-11 17:38:14 +0200368int register_spi_master(const struct spi_master *mst, void *data);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000369
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000370/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000371enum ich_chipset {
372 CHIPSET_ICH_UNKNOWN,
Stefan Tauner92d6a862013-10-25 00:33:37 +0000373 CHIPSET_ICH,
374 CHIPSET_ICH2345,
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000375 CHIPSET_ICH6,
Stefan Tauner92d6a862013-10-25 00:33:37 +0000376 CHIPSET_POULSBO, /* SCH U* */
377 CHIPSET_TUNNEL_CREEK, /* Atom E6xx */
378 CHIPSET_CENTERTON, /* Atom S1220 S1240 S1260 */
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000379 CHIPSET_ICH7,
Stefan Taunera8d838d2011-11-06 23:51:09 +0000380 CHIPSET_ICH8,
381 CHIPSET_ICH9,
382 CHIPSET_ICH10,
383 CHIPSET_5_SERIES_IBEX_PEAK,
384 CHIPSET_6_SERIES_COUGAR_POINT,
Stefan Tauner2abab942012-04-27 20:41:23 +0000385 CHIPSET_7_SERIES_PANTHER_POINT,
Duncan Laurie90eb2262013-03-15 03:12:29 +0000386 CHIPSET_8_SERIES_LYNX_POINT,
Duncan Laurie4095ed72014-08-20 15:39:32 +0000387 CHIPSET_BAYTRAIL, /* Actually all with Silvermont architecture: Bay Trail, Avoton/Rangeley */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000388 CHIPSET_8_SERIES_LYNX_POINT_LP,
389 CHIPSET_8_SERIES_WELLSBURG,
Duncan Laurie823096e2014-08-20 15:39:38 +0000390 CHIPSET_9_SERIES_WILDCAT_POINT,
Nico Huber51205912017-03-17 17:59:54 +0100391 CHIPSET_9_SERIES_WILDCAT_POINT_LP,
Nico Huber93c30692017-03-20 14:25:09 +0100392 CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
David Hendricksa5216362017-08-08 20:02:22 -0700393 CHIPSET_C620_SERIES_LEWISBURG,
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100394 CHIPSET_300_SERIES_CANNON_POINT,
Matt DeVillierb1f858f2020-08-12 12:48:06 -0500395 CHIPSET_400_SERIES_COMET_POINT,
Angel Pons59e344e2021-05-17 19:08:32 +0200396 CHIPSET_APOLLO_LAKE,
Angel Pons11a35982020-07-10 17:04:10 +0200397 CHIPSET_GEMINI_LAKE,
Stefan Taunera8d838d2011-11-06 23:51:09 +0000398};
399
Stefan Tauner2abab942012-04-27 20:41:23 +0000400/* ichspi.c */
401#if CONFIG_INTERNAL == 1
Nico Huber560111e2017-04-26 12:27:17 +0200402int ich_init_spi(void *spibar, enum ich_chipset ich_generation);
403int via_init_spi(uint32_t mmio_base);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000404
Stefan Taunerdbac46c2013-08-13 22:10:41 +0000405/* amd_imc.c */
Rudolf Marek70e14592013-07-25 22:58:56 +0000406int amd_imc_shutdown(struct pci_dev *dev);
407
David Hendricks4e748392011-02-28 23:58:15 +0000408/* it85spi.c */
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000409int it85xx_spi_init(struct superio s);
David Hendricks4e748392011-02-28 23:58:15 +0000410
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000411/* it87spi.c */
412void enter_conf_mode_ite(uint16_t port);
413void exit_conf_mode_ite(uint16_t port);
Carl-Daniel Hailfingerbfecef62011-04-27 14:34:08 +0000414void probe_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000415int init_superio_ite(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000416
David Hendricksf9a30552015-05-23 20:30:30 -0700417#if CONFIG_LINUX_MTD == 1
418/* trivial wrapper to avoid cluttering internal_init() with #if */
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200419static inline int try_mtd(void) { return programmer_linux_mtd.init(); };
David Hendricksf9a30552015-05-23 20:30:30 -0700420#else
421static inline int try_mtd(void) { return 1; };
422#endif
423
Carl-Daniel Hailfingerc4224842011-06-09 20:06:34 +0000424/* mcp6x_spi.c */
425int mcp6x_spi_init(int want_spi);
426
Thomas Heijligen508fb162021-06-10 15:17:53 +0200427
Victor Ding821e44c2020-08-18 18:27:26 +1000428
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000429/* sb600spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000430int sb600_probe_spi(struct pci_dev *dev);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000431
432/* wbsio_spi.c */
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000433int wbsio_check_for_spi(void);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000434#endif
435
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +0000436/* opaque.c */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000437struct opaque_master {
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +0000438 int max_data_read;
439 int max_data_write;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000440 /* Specific functions for this master */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000441 int (*probe) (struct flashctx *flash);
442 int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000443 int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000444 int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen);
Edward O'Callaghanec942502021-01-06 14:10:52 +1100445 void *data;
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +0000446};
Anastasia Klimchuk9309bed2021-05-13 12:28:47 +1000447int register_opaque_master(const struct opaque_master *mst, void *data);
Carl-Daniel Hailfinger532c7172011-11-04 21:35:26 +0000448
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000449/* programmer.c */
Stefan Tauner305e0b92013-07-17 23:46:44 +0000450void *fallback_map(const char *descr, uintptr_t phys_addr, size_t len);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000451void fallback_unmap(void *virt_addr, size_t len);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000452void fallback_chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr);
453void fallback_chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000454void fallback_chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000455uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr);
456uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr);
457void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000458struct par_master {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000459 void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr);
460 void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr);
461 void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000462 void (*chip_writen) (const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000463 uint8_t (*chip_readb) (const struct flashctx *flash, const chipaddr addr);
464 uint16_t (*chip_readw) (const struct flashctx *flash, const chipaddr addr);
465 uint32_t (*chip_readl) (const struct flashctx *flash, const chipaddr addr);
466 void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len);
Edward O'Callaghanec942502021-01-06 14:10:52 +1100467 void *data;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000468};
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000469int register_par_master(const struct par_master *mst, const enum chipbustype buses, void *data);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000470struct registered_master {
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000471 enum chipbustype buses_supported;
Edward O'Callaghan4eef6512021-02-03 11:19:41 +1100472 struct {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000473 struct par_master par;
474 struct spi_master spi;
475 struct opaque_master opaque;
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000476 };
477};
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000478extern struct registered_master registered_masters[];
479extern int registered_master_count;
Stefan Tauner5c316f92015-02-08 21:57:52 +0000480int register_master(const struct registered_master *mst);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000481
Thomas Heijligen508fb162021-06-10 15:17:53 +0200482
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000483
484/* serial.c */
Stefan Taunerb0eee9b2015-01-10 09:32:50 +0000485#if IS_WINDOWS
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000486typedef HANDLE fdtype;
Stefan Taunerbb4fed72012-09-01 21:47:19 +0000487#define SER_INV_FD INVALID_HANDLE_VALUE
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000488#else
489typedef int fdtype;
Stefan Taunerbb4fed72012-09-01 21:47:19 +0000490#define SER_INV_FD -1
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000491#endif
492
493void sp_flush_incoming(void);
Stefan Tauner72587f82016-01-04 03:05:15 +0000494fdtype sp_openserport(char *dev, int baud);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000495extern fdtype sp_fd;
Shawn Anastasio2b5adfb2017-12-31 00:17:15 -0600496int serialport_config(fdtype fd, int baud);
David Hendricks8bb20212011-06-14 01:35:36 +0000497int serialport_shutdown(void *data);
Mark Marshallf20b7be2014-05-09 21:16:21 +0000498int serialport_write(const unsigned char *buf, unsigned int writecnt);
499int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, unsigned int timeout, unsigned int *really_wrote);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000500int serialport_read(unsigned char *buf, unsigned int readcnt);
Stefan Tauner00e16082013-04-01 00:45:38 +0000501int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned int timeout, unsigned int *really_read);
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000502
Virgil-Adrian Teacada7c5452012-04-30 23:11:06 +0000503/* Serial port/pin mapping:
504
505 1 CD <-
506 2 RXD <-
507 3 TXD ->
508 4 DTR ->
509 5 GND --
510 6 DSR <-
511 7 RTS ->
512 8 CTS <-
513 9 RI <-
514*/
515enum SP_PIN {
516 PIN_CD = 1,
517 PIN_RXD,
518 PIN_TXD,
519 PIN_DTR,
520 PIN_GND,
521 PIN_DSR,
522 PIN_RTS,
523 PIN_CTS,
524 PIN_RI,
525};
526
527void sp_set_pin(enum SP_PIN pin, int val);
528int sp_get_pin(enum SP_PIN pin);
529
Nico Huber1cf407b2017-11-10 20:18:23 +0100530/* spi_master feature checks */
531static inline bool spi_master_4ba(const struct flashctx *const flash)
532{
533 return flash->mst->buses_supported & BUS_SPI &&
534 flash->mst->spi.features & SPI_MASTER_4BA;
535}
Nico Huberdc5af542018-12-22 16:54:59 +0100536static inline bool spi_master_no_4ba_modes(const struct flashctx *const flash)
537{
538 return flash->mst->buses_supported & BUS_SPI &&
539 flash->mst->spi.features & SPI_MASTER_NO_4BA_MODES;
540}
Nico Huber1cf407b2017-11-10 20:18:23 +0100541
Daniel Thompson1d507a02018-07-12 11:02:28 +0100542/* usbdev.c */
543struct libusb_device_handle;
544struct libusb_context;
545struct libusb_device_handle *usb_dev_get_by_vid_pid_serial(
546 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, const char *serialno);
547struct libusb_device_handle *usb_dev_get_by_vid_pid_number(
548 struct libusb_context *usb_ctx, uint16_t vid, uint16_t pid, unsigned int num);
549
Edward O'Callaghand97f87b2020-03-26 00:00:41 +1100550
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +0000551#endif /* !__PROGRAMMER_H__ */