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Uwe Hermannb4dcb712009-05-13 11:36:06 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermannb4dcb712009-05-13 11:36:06 +000015 */
16
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000017#if defined(__i386__) || defined(__x86_64__)
18
Uwe Hermannb4dcb712009-05-13 11:36:06 +000019#include <stdlib.h>
Uwe Hermannb4dcb712009-05-13 11:36:06 +000020#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000021#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000022#include "hwaccess.h"
Uwe Hermannb4dcb712009-05-13 11:36:06 +000023
24#define BIOS_ROM_ADDR 0x04
25#define BIOS_ROM_DATA 0x08
26#define INT_STATUS 0x0e
Uwe Hermann8403ccb2009-05-16 21:39:19 +000027#define INTERNAL_CONFIG 0x00
Uwe Hermannb4dcb712009-05-13 11:36:06 +000028#define SELECT_REG_WINDOW 0x800
29
Uwe Hermannb4dcb712009-05-13 11:36:06 +000030#define PCI_VENDOR_ID_3COM 0x10b7
31
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100032struct nic3com_data {
33 uint32_t io_base_addr;
34 uint32_t internal_conf;
35 uint16_t id;
36};
Uwe Hermann8403ccb2009-05-16 21:39:19 +000037
Thomas Heijligen4f5169d2021-05-04 15:32:17 +020038static const struct dev_entry nics_3com[] = {
Uwe Hermannb4dcb712009-05-13 11:36:06 +000039 /* 3C90xB */
Michael Karcher84486392010-02-24 00:04:40 +000040 {0x10b7, 0x9055, OK, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-TX"},
41 {0x10b7, 0x9001, NT, "3COM", "3C90xB: PCI 10/100 Mbps; shared 10BASE-T/100BASE-T4" },
42 {0x10b7, 0x9004, OK, "3COM", "3C90xB: PCI 10BASE-T (TPO)" },
43 {0x10b7, 0x9005, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2/AUI (COMBO)" },
44 {0x10b7, 0x9006, NT, "3COM", "3C90xB: PCI 10BASE-T/10BASE2 (TPC)" },
45 {0x10b7, 0x900a, NT, "3COM", "3C90xB: PCI 10BASE-FL" },
46 {0x10b7, 0x905a, NT, "3COM", "3C90xB: PCI 10BASE-FX" },
47 {0x10b7, 0x9058, OK, "3COM", "3C905B: Cyclone 10/100/BNC" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000048
49 /* 3C905C */
Michael Karcher84486392010-02-24 00:04:40 +000050 {0x10b7, 0x9200, OK, "3COM", "3C905C: EtherLink 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000051
52 /* 3C980C */
Michael Karcher84486392010-02-24 00:04:40 +000053 {0x10b7, 0x9805, NT, "3COM", "3C980C: EtherLink Server 10/100 PCI (TX)" },
Uwe Hermannb4dcb712009-05-13 11:36:06 +000054
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000055 {0},
Uwe Hermannb4dcb712009-05-13 11:36:06 +000056};
57
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000058static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100059 chipaddr addr)
60{
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100061 struct nic3com_data *data = flash->mst->par.data;
62
63 OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
64 OUTB(val, data->io_base_addr + BIOS_ROM_DATA);
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100065}
66
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000067static uint8_t nic3com_chip_readb(const struct flashctx *flash,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100068 const chipaddr addr)
69{
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100070 struct nic3com_data *data = flash->mst->par.data;
71
72 OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
73 return INB(data->io_base_addr + BIOS_ROM_DATA);
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100074}
75
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000076static const struct par_master par_master_nic3com = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000077 .chip_readb = nic3com_chip_readb,
78 .chip_readw = fallback_chip_readw,
79 .chip_readl = fallback_chip_readl,
80 .chip_readn = fallback_chip_readn,
81 .chip_writeb = nic3com_chip_writeb,
82 .chip_writew = fallback_chip_writew,
83 .chip_writel = fallback_chip_writel,
84 .chip_writen = fallback_chip_writen,
85};
86
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100087static int nic3com_shutdown(void *par_data)
David Hendricks8bb20212011-06-14 01:35:36 +000088{
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100089 struct nic3com_data *data = par_data;
90 const uint16_t id = data->id;
91
David Hendricks8bb20212011-06-14 01:35:36 +000092 /* 3COM 3C90xB cards need a special fixup. */
93 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
94 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
95 /* Select register window 3 and restore the receiver status. */
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +100096 OUTW(SELECT_REG_WINDOW + 3, data->io_base_addr + INT_STATUS);
97 OUTL(data->internal_conf, data->io_base_addr + INTERNAL_CONFIG);
David Hendricks8bb20212011-06-14 01:35:36 +000098 }
99
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +1000100 free(data);
David Hendricks8bb20212011-06-14 01:35:36 +0000101 return 0;
102}
103
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200104static int nic3com_init(void)
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000105{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000106 struct pci_dev *dev = NULL;
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +1000107 uint32_t io_base_addr = 0;
108 uint32_t internal_conf = 0;
109 uint16_t id;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000110
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000111 if (rget_io_perms())
112 return 1;
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000113
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000114 dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0);
115 if (!dev)
116 return 1;
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000117
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000118 io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000119 if (!io_base_addr)
120 return 1;
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000121
122 id = dev->device_id;
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000123
124 /* 3COM 3C90xB cards need a special fixup. */
125 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
Maciej Pijankabc2bbd22009-06-02 16:45:59 +0000126 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000127 /* Select register window 3 and save the receiver status. */
128 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
129 internal_conf = INL(io_base_addr + INTERNAL_CONFIG);
130
131 /* Set receiver type to MII for full BIOS ROM access. */
132 OUTL((internal_conf & 0xf00fffff) | 0x00600000, io_base_addr);
133 }
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000134
135 /*
136 * The lowest 16 bytes of the I/O mapped register space of (most) 3COM
137 * cards form a 'register window' into one of multiple (usually 8)
138 * register banks. For 3C90xB/3C90xC we need register window/bank 0.
139 */
140 OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
141
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +1000142 struct nic3com_data *data = calloc(1, sizeof(*data));
143 if (!data) {
144 msg_perr("Unable to allocate space for PAR master data\n");
145 goto init_err_cleanup_exit;
146 }
147 data->io_base_addr = io_base_addr;
148 data->internal_conf = internal_conf;
149 data->id = id;
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000150
151 max_rom_decode.parallel = 128 * 1024;
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +1000152
153 if (register_shutdown(nic3com_shutdown, data)) {
154 free(data);
155 goto init_err_cleanup_exit;
156 }
157 register_par_master(&par_master_nic3com, BUS_PARALLEL, data);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000158
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000159 return 0;
Anastasia Klimchukcedf7bd2021-06-01 11:17:17 +1000160
161init_err_cleanup_exit:
162 /* 3COM 3C90xB cards need a special fixup. */
163 if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005
164 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) {
165 /* Select register window 3 and restore the receiver status. */
166 OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS);
167 OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG);
168 }
169 return 1;
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000170}
171
Thomas Heijligen4f5169d2021-05-04 15:32:17 +0200172const struct programmer_entry programmer_nic3com = {
173 .name = "nic3com",
174 .type = PCI,
175 .devs.dev = nics_3com,
176 .init = nic3com_init,
177 .map_flash_region = fallback_map,
178 .unmap_flash_region = fallback_unmap,
179 .delay = internal_delay,
180};
181
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000182#else
183#error PCI port I/O access is not supported on this architecture yet.
184#endif