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Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2010,2011 Carl-Daniel Hailfinger
5 * Written by Carl-Daniel Hailfinger for Angelbird Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000015 */
16
17/* Datasheets are not public (yet?) */
Andrew Morgana0743832011-07-25 22:07:05 +000018#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000019
20#include <stdlib.h>
21#include "flash.h"
22#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000023#include "hwaccess.h"
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000024
Jacob Garberafc3ad62019-06-24 16:05:28 -060025static uint8_t *mv_bar;
26static uint16_t mv_iobar;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000027
Stefan Tauner4b24a2d2012-12-27 18:40:36 +000028const struct dev_entry satas_mv[] = {
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000029 /* 88SX6041 and 88SX6042 are the same according to the datasheet. */
30 {0x11ab, 0x7042, OK, "Marvell", "88SX7042 PCI-e 4-port SATA-II"},
31
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +000032 {0},
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000033};
34
35#define NVRAM_PARAM 0x1045c
36#define FLASH_PARAM 0x1046c
37#define EXPANSION_ROM_BAR_CONTROL 0x00d2c
38#define PCI_BAR2_CONTROL 0x00c08
39#define GPIO_PORT_CONTROL 0x104f0
40
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100041/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
42 * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
43 * This code only supports indirect accesses for now.
44 */
45
46/* Indirect access to via the I/O BAR1. */
47static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
48{
49 /* 0x80000000 selects BAR2 for remapping. */
50 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
51 OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
52}
53
54/* Indirect access to via the I/O BAR1. */
55static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
56{
57 /* 0x80000000 selects BAR2 for remapping. */
58 OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
59 return INB(mv_iobar + 0x80 + (addr & 0x3));
60}
61
62/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000063static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100064 chipaddr addr)
65{
66 satamv_indirect_chip_writeb(val, addr);
67}
68
69/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000070static uint8_t satamv_chip_readb(const struct flashctx *flash,
Edward O'Callaghanad8eb602021-05-24 20:33:45 +100071 const chipaddr addr)
72{
73 return satamv_indirect_chip_readb(addr);
74}
75
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +000076static const struct par_master par_master_satamv = {
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +000077 .chip_readb = satamv_chip_readb,
78 .chip_readw = fallback_chip_readw,
79 .chip_readl = fallback_chip_readl,
80 .chip_readn = fallback_chip_readn,
81 .chip_writeb = satamv_chip_writeb,
82 .chip_writew = fallback_chip_writew,
83 .chip_writel = fallback_chip_writel,
84 .chip_writen = fallback_chip_writen,
85};
86
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +000087/*
88 * Random notes:
89 * FCE# Flash Chip Enable
90 * FWE# Flash Write Enable
91 * FOE# Flash Output Enable
92 * FALE[1:0] Flash Address Latch Enable
93 * FAD[7:0] Flash Multiplexed Address/Data Bus
94 * FA[2:0] Flash Address Low
95 *
96 * GPIO[15,2] GPIO Port Mode
97 * GPIO[4:3] Flash Size
98 *
99 * 0xd2c Expansion ROM BAR Control
100 * 0xc08 PCI BAR2 (Flash/NVRAM) Control
101 * 0x1046c Flash Parameters
102 */
103int satamv_init(void)
104{
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000105 struct pci_dev *dev = NULL;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000106 uintptr_t addr;
107 uint32_t tmp;
108
Carl-Daniel Hailfingerd6bb8282012-07-21 17:27:08 +0000109 if (rget_io_perms())
110 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000111
112 /* BAR0 has all internal registers memory mapped. */
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000113 dev = pcidev_init(satas_mv, PCI_BASE_ADDRESS_0);
114 if (!dev)
115 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000116
Carl-Daniel Hailfingera2faddf2013-01-05 23:52:45 +0000117 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000118 if (!addr)
119 return 1;
120
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000121 mv_bar = rphysmap("Marvell 88SX7042 registers", addr, 0x20000);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000122 if (mv_bar == ERROR_PTR)
Stefan Tauner55619552013-01-04 22:24:58 +0000123 return 1;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000124
125 tmp = pci_mmio_readl(mv_bar + FLASH_PARAM);
126 msg_pspew("Flash Parameters:\n");
127 msg_pspew("TurnOff=0x%01x\n", (tmp >> 0) & 0x7);
128 msg_pspew("Acc2First=0x%01x\n", (tmp >> 3) & 0xf);
129 msg_pspew("Acc2Next=0x%01x\n", (tmp >> 7) & 0xf);
130 msg_pspew("ALE2Wr=0x%01x\n", (tmp >> 11) & 0x7);
131 msg_pspew("WrLow=0x%01x\n", (tmp >> 14) & 0x7);
132 msg_pspew("WrHigh=0x%01x\n", (tmp >> 17) & 0x7);
133 msg_pspew("Reserved[21:20]=0x%01x\n", (tmp >> 20) & 0x3);
134 msg_pspew("TurnOffExt=0x%01x\n", (tmp >> 22) & 0x1);
135 msg_pspew("Acc2FirstExt=0x%01x\n", (tmp >> 23) & 0x1);
136 msg_pspew("Acc2NextExt=0x%01x\n", (tmp >> 24) & 0x1);
137 msg_pspew("ALE2WrExt=0x%01x\n", (tmp >> 25) & 0x1);
138 msg_pspew("WrLowExt=0x%01x\n", (tmp >> 26) & 0x1);
139 msg_pspew("WrHighExt=0x%01x\n", (tmp >> 27) & 0x1);
140 msg_pspew("Reserved[31:28]=0x%01x\n", (tmp >> 28) & 0xf);
141
142 tmp = pci_mmio_readl(mv_bar + EXPANSION_ROM_BAR_CONTROL);
143 msg_pspew("Expansion ROM BAR Control:\n");
144 msg_pspew("ExpROMSz=0x%01x\n", (tmp >> 19) & 0x7);
145
146 /* Enable BAR2 mapping to flash */
147 tmp = pci_mmio_readl(mv_bar + PCI_BAR2_CONTROL);
148 msg_pspew("PCI BAR2 (Flash/NVRAM) Control:\n");
149 msg_pspew("Bar2En=0x%01x\n", (tmp >> 0) & 0x1);
150 msg_pspew("BAR2TransAttr=0x%01x\n", (tmp >> 1) & 0x1f);
151 msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7);
152 tmp &= 0xffffffc0;
153 tmp |= 0x0000001f;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000154 pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000155
156 /* Enable flash: GPIO Port Control Register 0x104f0 */
157 tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL);
158 msg_pspew("GPIOPortMode=0x%01x\n", (tmp >> 0) & 0x3);
159 if (((tmp >> 0) & 0x3) != 0x2)
160 msg_pinfo("Warning! Either the straps are incorrect or you "
161 "have no flash or someone overwrote the strap "
162 "values!\n");
163 tmp &= 0xfffffffc;
164 tmp |= 0x2;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000165 pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000166
167 /* Get I/O BAR location. */
Stefan Reinauer789ea5e2014-04-26 16:12:15 +0000168 addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2);
Niklas Söderlund89edf362013-08-23 23:29:23 +0000169 if (!addr)
170 return 1;
171
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000172 /* Truncate to reachable range.
173 * FIXME: Check if the I/O BAR is actually reachable.
174 * This is an arch specific check.
175 */
Stefan Reinauer789ea5e2014-04-26 16:12:15 +0000176 mv_iobar = addr & 0xffff;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000177 msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
178
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000179 /* 512 kByte with two 8-bit latches, and
180 * 4 MByte with additional 3-bit latch. */
181 max_rom_decode.parallel = 4 * 1024 * 1024;
Anastasia Klimchuk6a5db262021-05-21 09:40:58 +1000182 register_par_master(&par_master_satamv, BUS_PARALLEL, NULL);
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000183
184 return 0;
Carl-Daniel Hailfinger9a1105c2011-02-04 21:37:59 +0000185}
186
Andrew Morgana0743832011-07-25 22:07:05 +0000187#else
188#error PCI port I/O access is not supported on this architecture yet.
189#endif