blob: b4ec96b0bfe1991dff1de87ffa4f3e10d0d4f14b [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000033#include <inttypes.h>
34#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000036#include "programmer.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000040#if defined(__i386__) || defined(__x86_64__)
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000052 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000053
54 return 0;
55}
56
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000057static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 tmp = pci_read_byte(dev, 0xd0);
62 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000063 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000064
65 return 0;
66}
67
68static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
69{
70 uint8_t new, newer;
71
72 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
73 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
74 new = pci_read_byte(dev, 0x40);
75 new &= (~0x04); /* No idea why we clear bit 2. */
76 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000077 rpci_write_byte(dev, 0x40, new);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000078 newer = pci_read_byte(dev, 0x40);
79 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +000080 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
81 "(WARNING ONLY).\n", 0x40, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +000082 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000083 return -1;
84 }
85 return 0;
86}
87
88static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
89{
90 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +000091
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000092 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
93 if (!sbdev)
94 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
95 if (!sbdev)
96 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
97 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000098 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000099 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000100 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000101 sbdev->vendor_id, sbdev->device_id,
102 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000103 return sbdev;
104}
105
106static int enable_flash_sis501(struct pci_dev *dev, const char *name)
107{
108 uint8_t tmp;
109 int ret = 0;
110 struct pci_dev *sbdev;
111
112 sbdev = find_southbridge(dev->vendor_id, name);
113 if (!sbdev)
114 return -1;
115
116 ret = enable_flash_sis_mapping(sbdev, name);
117
118 tmp = sio_read(0x22, 0x80);
119 tmp &= (~0x20);
120 tmp |= 0x4;
121 sio_write(0x22, 0x80, tmp);
122
123 tmp = sio_read(0x22, 0x70);
124 tmp &= (~0x20);
125 tmp |= 0x4;
126 sio_write(0x22, 0x70, tmp);
127
128 return ret;
129}
130
131static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
132{
133 uint8_t tmp;
134 int ret = 0;
135 struct pci_dev *sbdev;
136
137 sbdev = find_southbridge(dev->vendor_id, name);
138 if (!sbdev)
139 return -1;
140
141 ret = enable_flash_sis_mapping(sbdev, name);
142
143 tmp = sio_read(0x22, 0x50);
144 tmp &= (~0x20);
145 tmp |= 0x4;
146 sio_write(0x22, 0x50, tmp);
147
148 return ret;
149}
150
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000151static int enable_flash_sis530(struct pci_dev *dev, const char *name)
152{
153 uint8_t new, newer;
154 int ret = 0;
155 struct pci_dev *sbdev;
156
157 sbdev = find_southbridge(dev->vendor_id, name);
158 if (!sbdev)
159 return -1;
160
161 ret = enable_flash_sis_mapping(sbdev, name);
162
163 new = pci_read_byte(sbdev, 0x45);
164 new &= (~0x20);
165 new |= 0x4;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000166 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000167 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000168 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000169 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
170 "(WARNING ONLY).\n", 0x45, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +0000171 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000172 ret = -1;
173 }
174
175 return ret;
176}
177
178static int enable_flash_sis540(struct pci_dev *dev, const char *name)
179{
180 uint8_t new, newer;
181 int ret = 0;
182 struct pci_dev *sbdev;
183
184 sbdev = find_southbridge(dev->vendor_id, name);
185 if (!sbdev)
186 return -1;
187
188 ret = enable_flash_sis_mapping(sbdev, name);
189
190 new = pci_read_byte(sbdev, 0x45);
191 new &= (~0x80);
192 new |= 0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000193 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000194 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000195 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000196 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
197 "(WARNING ONLY).\n", 0x45, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +0000198 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000199 ret = -1;
200 }
201
202 return ret;
203}
204
Uwe Hermann987942d2006-11-07 11:16:21 +0000205/* Datasheet:
206 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
207 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
208 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
209 * - Order Number: 290562-001
210 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000211static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000212{
213 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000214 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000215
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000216 buses_supported = BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000217
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000218 old = pci_read_word(dev, xbcs);
219
220 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000221 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000222 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000223 * Set bit 7: Extended BIOS Enable (PCI master accesses to
224 * FFF80000-FFFDFFFF are forwarded to ISA).
225 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
226 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
227 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
228 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
229 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
230 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
231 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000232 if (dev->device_id == 0x122e || dev->device_id == 0x7000
233 || dev->device_id == 0x1234)
234 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000235 else
236 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000237
238 if (new == old)
239 return 0;
240
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000241 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000242
243 if (pci_read_word(dev, xbcs) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000244 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
245 "(WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000246 return -1;
247 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000248
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000249 return 0;
250}
251
Uwe Hermann372eeb52007-12-04 21:49:06 +0000252/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000253 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
254 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000255 */
256static int enable_flash_ich(struct pci_dev *dev, const char *name,
257 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000258{
Ollie Lho184a4042005-11-26 21:55:36 +0000259 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000260
Uwe Hermann372eeb52007-12-04 21:49:06 +0000261 /*
262 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000263 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000264 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000265 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000266
Sean Nelson316a29f2010-05-07 20:09:04 +0000267 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000268 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000269 msg_pdbg("BIOS Write Enable: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000270 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000271 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000272
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000273 /*
274 * Quote from the 6 Series datasheet (Document Number: 324645-004):
275 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
276 * 1 = BIOS region SMM protection is enabled.
277 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000278 * In earlier chipsets this bit is reserved.
279 */
280 if (old & (1 << 5))
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000281 msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000282
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000283 new = old | 1;
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000284 if (new == old)
285 return 0;
286
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000287 rpci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000288
Stefan Reinauer86de2832006-03-31 11:26:55 +0000289 if (pci_read_byte(dev, bios_cntl) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000290 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
291 "(WARNING ONLY).\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000292 return -1;
293 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000294
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000295 return 0;
296}
297
Uwe Hermann372eeb52007-12-04 21:49:06 +0000298static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000299{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000300 /*
301 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
302 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
303 * FB_DEC_EN2.
304 */
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000305 buses_supported = BUS_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000306 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000307}
308
Uwe Hermann372eeb52007-12-04 21:49:06 +0000309static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000310{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000311 uint32_t fwh_conf;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000312 char *idsel = NULL;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000313 int i, tmp, max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000314 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000315
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000316 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000317 if (idsel && strlen(idsel)) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000318 uint64_t fwh_idsel_old, fwh_idsel;
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000319 errno = 0;
320 /* Base 16, nothing else makes sense. */
321 fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
322 if (errno) {
323 msg_perr("Error: fwh_idsel= specified, but value could "
324 "not be converted.\n");
325 goto idsel_garbage_out;
326 }
327 if (fwh_idsel & 0xffff000000000000ULL) {
328 msg_perr("Error: fwh_idsel= specified, but value had "
329 "unusued bits set.\n");
330 goto idsel_garbage_out;
331 }
332 fwh_idsel_old = pci_read_long(dev, 0xd0);
333 fwh_idsel_old <<= 16;
334 fwh_idsel_old |= pci_read_word(dev, 0xd4);
335 msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to "
336 "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old,
337 fwh_idsel);
338 rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
339 rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000340 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000341 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000342 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
343idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000344 free(idsel);
345 /* FIXME: Return failure here once internal_init() starts
346 * to care about the return value of the chipset enable.
347 */
348 exit(1);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000349 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000350 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000351
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000352 /* Ignore all legacy ranges below 1 MB.
353 * We currently only support flashing the chip which responds to
354 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
355 * have to be adjusted.
356 */
357 /* FWH_SEL1 */
358 fwh_conf = pci_read_long(dev, 0xd0);
359 for (i = 7; i >= 0; i--) {
360 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000361 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000362 (0x1ff8 + i) * 0x80000,
363 (0x1ff0 + i) * 0x80000,
364 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000365 if ((tmp == 0) && contiguous) {
366 max_decode_fwh_idsel = (8 - i) * 0x80000;
367 } else {
368 contiguous = 0;
369 }
370 }
371 /* FWH_SEL2 */
372 fwh_conf = pci_read_word(dev, 0xd4);
373 for (i = 3; i >= 0; i--) {
374 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000375 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000376 (0xff4 + i) * 0x100000,
377 (0xff0 + i) * 0x100000,
378 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000379 if ((tmp == 0) && contiguous) {
380 max_decode_fwh_idsel = (8 - i) * 0x100000;
381 } else {
382 contiguous = 0;
383 }
384 }
385 contiguous = 1;
386 /* FWH_DEC_EN1 */
387 fwh_conf = pci_read_word(dev, 0xd8);
388 for (i = 7; i >= 0; i--) {
389 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000390 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000391 (0x1ff8 + i) * 0x80000,
392 (0x1ff0 + i) * 0x80000,
393 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000394 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000395 max_decode_fwh_decode = (8 - i) * 0x80000;
396 } else {
397 contiguous = 0;
398 }
399 }
400 for (i = 3; i >= 0; i--) {
401 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000402 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000403 (0xff4 + i) * 0x100000,
404 (0xff0 + i) * 0x100000,
405 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000406 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000407 max_decode_fwh_decode = (8 - i) * 0x100000;
408 } else {
409 contiguous = 0;
410 }
411 }
412 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000413 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000414
415 /* If we're called by enable_flash_ich_dc_spi, it will override
416 * buses_supported anyway.
417 */
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000418 buses_supported = BUS_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000419 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000420}
421
Adam Jurkowskie4984102009-12-21 15:30:46 +0000422static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
423{
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000424 uint16_t old, new;
425 int err;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000426
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000427 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
428 return err;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000429
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000430 old = pci_read_byte(dev, 0xd9);
431 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
432 (old & 1) ? "en" : "dis");
433 new = old & ~1;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000434
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000435 if (new != old)
436 rpci_write_byte(dev, 0xd9, new);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000437
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000438 buses_supported = BUS_FWH;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000439 return 0;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000440}
441
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000442#define ICH_STRAP_RSVD 0x00
443#define ICH_STRAP_SPI 0x01
444#define ICH_STRAP_PCI 0x02
445#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000446
Uwe Hermann394131e2008-10-18 21:14:13 +0000447static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
448{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000449 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000450 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000451}
452
Uwe Hermann394131e2008-10-18 21:14:13 +0000453static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
454 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000455{
Michael Karchera4448d92010-07-22 18:04:15 +0000456 int ret;
457 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000458 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000459 void *rcrb;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000460
461 /*
462 * TODO: These names are incorrect for EP80579. For that, the solution
463 * would look like the commented line below.
464 */
465 // static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000466 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000467
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000468 /* Enable Flash Writes */
469 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000470
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000471 /* Get physical address of Root Complex Register Block */
472 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000473 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000474
475 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000476 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000477
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000478 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000479 msg_pdbg("GCS = 0x%x: ", gcs);
480 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000481 (gcs & 0x1) ? "en" : "dis");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000482 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000483 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000484
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000485 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000486 msg_pdbg("Top Swap : %s\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000487 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000488
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000489 /* It seems the ICH7 does not support SPI and LPC chips at the same
490 * time. At least not with our current code. So we prevent searching
491 * on ICH7 when the southbridge is strapped to LPC
492 */
493
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000494 buses_supported = BUS_FWH;
Michael Karchera4448d92010-07-22 18:04:15 +0000495 if (ich_generation == 7) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000496 if (bbs == ICH_STRAP_LPC) {
Michael Karchera4448d92010-07-22 18:04:15 +0000497 /* No further SPI initialization required */
498 return ret;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000499 } else {
Michael Karchera4448d92010-07-22 18:04:15 +0000500 /* Disable LPC/FWH if strapped to PCI or SPI */
501 buses_supported = 0;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000502 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000503 }
504
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000505 /* This adds BUS_SPI */
Michael Karchera4448d92010-07-22 18:04:15 +0000506 if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000507 if (!ret)
508 ret = ERROR_NONFATAL;
509 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000510
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000511 return ret;
512}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000513
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000514static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000515{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000516 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000517}
518
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000519static int enable_flash_ich8(struct pci_dev *dev, const char *name)
520{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000521 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000522}
523
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000524static int enable_flash_ich9(struct pci_dev *dev, const char *name)
525{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000526 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000527}
528
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000529static int enable_flash_ich10(struct pci_dev *dev, const char *name)
530{
531 return enable_flash_ich_dc_spi(dev, name, 10);
532}
533
Michael Karcher89bed6d2010-06-13 10:16:12 +0000534static int via_no_byte_merge(struct pci_dev *dev, const char *name)
535{
536 uint8_t val;
537
538 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000539 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +0000540 msg_pdbg("Disabling byte merging\n");
541 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000542 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000543 }
544 return NOT_DONE_YET; /* need to find south bridge, too */
545}
546
Uwe Hermann372eeb52007-12-04 21:49:06 +0000547static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000548{
Ollie Lho184a4042005-11-26 21:55:36 +0000549 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000550
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000551 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000552 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000553
Uwe Hermannffec5f32007-08-23 16:08:21 +0000554 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000555 val = pci_read_byte(dev, 0x40);
556 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000557 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000558
559 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000560 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000561 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000562 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000563 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000564
Luc Verhaegen73d21192009-12-23 00:54:26 +0000565 if (dev->device_id == 0x3227) { /* VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000566 /* All memory cycles, not just ROM ones, go to LPC. */
567 val = pci_read_byte(dev, 0x59);
568 val &= ~0x80;
569 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000570 }
571
Uwe Hermanna7e05482007-05-09 10:17:44 +0000572 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000573}
574
Uwe Hermann372eeb52007-12-04 21:49:06 +0000575static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000576{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000577 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000578
Uwe Hermann394131e2008-10-18 21:14:13 +0000579#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
580#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000581#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
582#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000583
Uwe Hermann394131e2008-10-18 21:14:13 +0000584#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
585#define ROM_WRITE_ENABLE (1 << 1)
586#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
587#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000588#define CS5530_ISA_MASTER (1 << 7)
589#define CS5530_ENABLE_SA2320 (1 << 2)
590#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000591
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000592 buses_supported = BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000593 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
594 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000595 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
596 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000597 * Make the configured ROM areas writable.
598 */
599 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
600 reg8 |= LOWER_ROM_ADDRESS_RANGE;
601 reg8 |= UPPER_ROM_ADDRESS_RANGE;
602 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000603 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000604
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000605 /* Set positive decode on ROM. */
606 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
607 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000608 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000609
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000610 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
611 if (reg8 & CS5530_ISA_MASTER) {
612 /* We have A0-A23 available. */
613 max_rom_decode.parallel = 16 * 1024 * 1024;
614 } else {
615 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
616 if (reg8 & CS5530_ENABLE_SA2320) {
617 /* We have A0-19, A20-A23 available. */
618 max_rom_decode.parallel = 16 * 1024 * 1024;
619 } else if (reg8 & CS5530_ENABLE_SA20) {
620 /* We have A0-19, A20 available. */
621 max_rom_decode.parallel = 2 * 1024 * 1024;
622 } else {
623 /* A20 and above are not active. */
624 max_rom_decode.parallel = 1024 * 1024;
625 }
626 }
627
Ollie Lhocbbf1252004-03-17 22:22:08 +0000628 return 0;
629}
630
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000631/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000632 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000633 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000634 *
635 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
636 * To enable write to NOR Boot flash for the benefit of systems that have such
637 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000638 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000639static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000640{
Uwe Hermann394131e2008-10-18 21:14:13 +0000641#define MSR_RCONF_DEFAULT 0x1808
642#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000643
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000644 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000645
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000646 /* Geode only has a single core */
647 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000648 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000649
650 msr = rdmsr(MSR_RCONF_DEFAULT);
651 if ((msr.hi >> 24) != 0x22) {
652 msr.hi &= 0xfbffffff;
653 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000654 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000655
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000656 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000657 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000658 msr.lo |= 0x08;
659 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000660
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000661 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000662
Uwe Hermann394131e2008-10-18 21:14:13 +0000663#undef MSR_RCONF_DEFAULT
664#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000665 return 0;
666}
667
Uwe Hermann372eeb52007-12-04 21:49:06 +0000668static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000669{
Ollie Lho184a4042005-11-26 21:55:36 +0000670 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000671
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000672 rpci_write_byte(dev, 0x52, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000673
674 new = pci_read_byte(dev, 0x52);
675
676 if (new != 0xee) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000677 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
678 "(WARNING ONLY).\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000679 return -1;
680 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000681
Ollie Lhocbbf1252004-03-17 22:22:08 +0000682 return 0;
683}
684
Uwe Hermann190f8492008-10-25 18:03:50 +0000685/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000686static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000687{
Ollie Lho184a4042005-11-26 21:55:36 +0000688 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000689
Uwe Hermann372eeb52007-12-04 21:49:06 +0000690 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000691 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000692 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000693 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000694 rpci_write_byte(dev, 0x43, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000695 if (pci_read_byte(dev, 0x43) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000696 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
697 "(WARNING ONLY).\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000698 }
699 }
700
Uwe Hermann190f8492008-10-25 18:03:50 +0000701 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000702 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000703 new = old | 0x01;
704 if (new == old)
705 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000706 rpci_write_byte(dev, 0x40, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000707
708 if (pci_read_byte(dev, 0x40) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000709 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
710 "(WARNING ONLY).\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000711 return -1;
712 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000713
Ollie Lhocbbf1252004-03-17 22:22:08 +0000714 return 0;
715}
716
Marc Jones3af487d2008-10-15 17:50:29 +0000717static int enable_flash_sb600(struct pci_dev *dev, const char *name)
718{
Michael Karcherb05b9e12010-07-22 18:04:19 +0000719 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000720 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000721 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000722
Jason Wanga3f04be2008-11-28 21:36:51 +0000723 /* Clear ROM protect 0-3. */
724 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000725 prot = pci_read_long(dev, reg);
726 /* No protection flags for this region?*/
727 if ((prot & 0x3) == 0)
728 continue;
Mathias Krause9fbdc032011-01-01 10:54:09 +0000729 msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000730 (prot & 0x1) ? "write " : "",
731 (prot & 0x2) ? "read " : "",
732 (prot & 0xfffff800),
733 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000734 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000735 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000736 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000737 if (prot & 0x3)
Mathias Krause9fbdc032011-01-01 10:54:09 +0000738 msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000739 (prot & 0x1) ? "write " : "",
740 (prot & 0x2) ? "read " : "",
741 (prot & 0xfffff800),
742 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Jason Wanga3f04be2008-11-28 21:36:51 +0000743 }
744
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000745 buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000746
747 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +0000748
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000749 /* Read ROM strap override register. */
750 OUTB(0x8f, 0xcd6);
751 reg = INB(0xcd7);
752 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000753 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000754 if (reg & 0x02) {
755 switch ((reg & 0x0c) >> 2) {
756 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000757 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000758 break;
759 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000760 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000761 break;
762 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000763 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000764 break;
765 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000766 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000767 break;
768 }
769 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000770 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000771
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000772 /* Force enable SPI ROM in SB600 PM register.
773 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000774 * But how can we know which ROM we are going to handle? So we have
775 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000776 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
777 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000778 */
779 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000780 OUTB(0x8f, 0xcd6);
781 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000782 */
Marc Jones3af487d2008-10-15 17:50:29 +0000783
Michael Karcherb05b9e12010-07-22 18:04:19 +0000784 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000785}
786
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000787static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
788{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000789 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000790
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000791 rpci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000792
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000793 tmp = pci_read_byte(dev, 0x6d);
794 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000795 rpci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000796
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000797 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000798}
799
Uwe Hermann372eeb52007-12-04 21:49:06 +0000800static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000801{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000802 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000803
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +0000804 pci_write_byte(dev, 0x92, 0x00);
805 if (pci_read_byte(dev, 0x92) != 0x00) {
806 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
807 "(WARNING ONLY).\n", 0x92, 0x00, name);
808 }
809
Uwe Hermanna7e05482007-05-09 10:17:44 +0000810 old = pci_read_byte(dev, 0x88);
811 new = old | 0xc0;
812 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000813 rpci_write_byte(dev, 0x88, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814 if (pci_read_byte(dev, 0x88) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000815 msg_pinfo("Setting register to set 0x%x to 0x%x on %s "
816 "failed (WARNING ONLY).\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000817 }
818 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000819
Uwe Hermanna7e05482007-05-09 10:17:44 +0000820 old = pci_read_byte(dev, 0x6d);
821 new = old | 0x01;
822 if (new == old)
823 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000824 rpci_write_byte(dev, 0x6d, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000825
826 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000827 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
828 "(WARNING ONLY).\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000829 return -1;
830 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000831
Uwe Hermanna7e05482007-05-09 10:17:44 +0000832 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000833}
834
Joshua Roys85835d82010-09-15 14:47:56 +0000835static int enable_flash_osb4(struct pci_dev *dev, const char *name)
836{
837 uint8_t tmp;
838
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000839 buses_supported = BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +0000840
841 tmp = INB(0xc06);
842 tmp |= 0x1;
843 OUTB(tmp, 0xc06);
844
845 tmp = INB(0xc6f);
846 tmp |= 0x40;
847 OUTB(tmp, 0xc6f);
848
849 return 0;
850}
851
Uwe Hermann372eeb52007-12-04 21:49:06 +0000852/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
853static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000854{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000855 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000856 struct pci_dev *smbusdev;
857
Uwe Hermann372eeb52007-12-04 21:49:06 +0000858 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000859 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000860
Uwe Hermanna7e05482007-05-09 10:17:44 +0000861 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000862 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000863 exit(1);
864 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000865
Uwe Hermann372eeb52007-12-04 21:49:06 +0000866 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000867 tmp = pci_read_byte(smbusdev, 0x79);
868 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000869 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000870
Uwe Hermann372eeb52007-12-04 21:49:06 +0000871 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000872 tmp = pci_read_byte(dev, 0x48);
873 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000874 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000875
Uwe Hermann372eeb52007-12-04 21:49:06 +0000876 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000877 tmp = INB(0xc6f);
878 OUTB(tmp, 0xeb);
879 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000880 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000881 OUTB(tmp, 0xc6f);
882 OUTB(tmp, 0xeb);
883 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000884
885 return 0;
886}
887
Uwe Hermann372eeb52007-12-04 21:49:06 +0000888static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000889{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000890 uint8_t old, new, val;
891 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000892
Uwe Hermann372eeb52007-12-04 21:49:06 +0000893 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000894 val = pci_read_byte(dev, 0x88);
895 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000896 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000897 val = pci_read_byte(dev, 0x8c);
898 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000899 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000900 wordval = pci_read_word(dev, 0x90);
901 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000902 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000903
Uwe Hermanna7e05482007-05-09 10:17:44 +0000904 old = pci_read_byte(dev, 0x6d);
905 new = old | 0x01;
906 if (new == old)
907 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000908 rpci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000909
Uwe Hermanna7e05482007-05-09 10:17:44 +0000910 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000911 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
912 "(WARNING ONLY).\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000913 return -1;
914 }
Yinghai Luca782972007-01-22 20:21:17 +0000915
916 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000917}
918
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000919/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000920 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
921 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
922 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000923 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000924static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000925{
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000926 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +0000927 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000928
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000929 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
930
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000931 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000932 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000933 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +0000934 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000935
Michael Karchercfa674f2010-02-25 11:38:23 +0000936 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000937 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000938 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000939 buses_supported = BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000940 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000941 break;
942 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000943 want_spi = 1;
944 /* SPI is added in mcp6x_spi_init if it works.
945 * Do we really want to disable LPC in this case?
946 */
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000947 buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000948 msg_pdbg("Flash bus type is SPI\n");
Stefan Tauner25b5a592011-07-13 20:48:54 +0000949 msg_pinfo("SPI on this chipset is WIP. Please report any "
950 "success or failure by mailing us the verbose "
951 "output to flashrom@flashrom.org, thanks!\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000952 break;
953 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000954 /* Should not happen. */
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +0000955 buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000956 msg_pdbg("Flash bus type is unknown (none)\n");
957 msg_pinfo("Something went wrong with bus type detection.\n");
958 goto out_msg;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000959 break;
960 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000961
962 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000963#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +0000964 val |= (1 << 6);
965 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000966 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000967#endif
968
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000969 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000970 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000971
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000972out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000973 msg_pinfo("Please send the output of \"flashrom -V\" to "
Paul Menzelab6328f2010-10-08 11:03:02 +0000974 "flashrom@flashrom.org with\n"
975 "your board name: flashrom -V as the subject to help us "
976 "finish support for your\n"
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000977 "chipset. Thanks.\n");
978
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000979 return ret;
980}
981
Uwe Hermann372eeb52007-12-04 21:49:06 +0000982static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000983{
Michael Karchercfa674f2010-02-25 11:38:23 +0000984 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000985
Uwe Hermanne823ee02007-06-05 15:02:18 +0000986 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000987 val = pci_read_byte(dev, 0x41);
988 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000989 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000990
Michael Karchercfa674f2010-02-25 11:38:23 +0000991 val = pci_read_byte(dev, 0x43);
992 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000993 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000994
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000995 return 0;
996}
997
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000998/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000999 * Usually on the x86 architectures (and on other PC-like platforms like some
1000 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1001 * Elan SC520 only a small piece of the system flash is mapped there, but the
1002 * complete flash is mapped somewhere below 1G. The position can be determined
1003 * by the BOOTCS PAR register.
1004 */
1005static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1006{
1007 int i, bootcs_found = 0;
1008 uint32_t parx = 0;
1009 void *mmcr;
1010
1011 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001012 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001013
1014 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1015 * BOOTCS region (PARx[31:29] = 100b)e
1016 */
1017 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001018 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001019 if ((parx >> 29) == 4) {
1020 bootcs_found = 1;
1021 break; /* BOOTCS found */
1022 }
1023 }
1024
1025 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1026 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1027 */
1028 if (bootcs_found) {
1029 if (parx & (1 << 25)) {
1030 parx &= (1 << 14) - 1; /* Mask [13:0] */
1031 flashbase = parx << 16;
1032 } else {
1033 parx &= (1 << 18) - 1; /* Mask [17:0] */
1034 flashbase = parx << 12;
1035 }
1036 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001037 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
1038 "Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001039 }
1040
1041 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001042 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001043 return 0;
1044}
1045
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001046#endif
1047
Idwer Vollering326a0602011-06-18 18:45:41 +00001048/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001049const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001050#if defined(__i386__) || defined(__x86_64__)
Idwer Vollering326a0602011-06-18 18:45:41 +00001051 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001052 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
Stefan Tauner77000512011-04-02 11:47:21 +00001053 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001054 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
Idwer Vollering326a0602011-06-18 18:45:41 +00001055 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1056 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1057 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1058 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1059 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1060 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1061 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1062 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1063 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1064 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1065 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1066 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1067 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1068 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001069 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001070 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1071 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001072 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001073 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1074 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
1075 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1076 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1077 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1078 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1079 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1080 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1081 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1082 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1083 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
1084 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1085 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1086 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1087 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1088 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1089 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1090 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001091 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
Stefan Taunerd06d9412011-06-12 19:47:55 +00001092 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001093 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1094 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Stefan Taunerd06d9412011-06-12 19:47:55 +00001095 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1096 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001097 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001098 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001099 {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804},
Uwe Hermannb0039912009-05-07 13:24:49 +00001100 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1101 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1102 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1103 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001104 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1105 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1106 * Until we have PCI device class matching or some fallback mechanism,
1107 * this is needed to get flashrom working on Tyan S2915 and maybe other
1108 * dual-MCP55 boards.
1109 */
1110#if 0
1111 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1112#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001113 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1114 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1115 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1116 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1117 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1118 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001119 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1120 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1121 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1122 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1123 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1124 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1125 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1126 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1127 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1128 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1129 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1130 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1131 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1132 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1133 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1134 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001135 /* VIA northbridges */
1136 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1137 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1138 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001139 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
Idwer Vollering326a0602011-06-18 18:45:41 +00001140 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
Michael Karcher89bed6d2010-06-13 10:16:12 +00001141 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1142 /* VIA southbridges */
Idwer Vollering326a0602011-06-18 18:45:41 +00001143 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1144 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
1145 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001146 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001147 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001148 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1149 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1150 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1151 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Idwer Vollering326a0602011-06-18 18:45:41 +00001152 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1153 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001154 {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi},
1155 {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt823x},
Idwer Vollering326a0602011-06-18 18:45:41 +00001156 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1157 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1158 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1159 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
Stefan Tauner2cf2da62011-06-18 18:45:56 +00001160 {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_ich10},
1161 {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_ich10},
1162 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_ich10},
1163 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_ich10},
1164 {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_ich10},
1165 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_ich10},
1166 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_ich10},
1167 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_ich10},
1168 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_ich10},
1169 {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_ich10},
1170 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_ich10},
1171 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_ich10},
1172 {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_ich10},
1173 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_ich10},
1174 {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001175 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
1176 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
1177 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1178 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001179 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich_4e},
Idwer Vollering326a0602011-06-18 18:45:41 +00001180 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
1181 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
1182 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1183 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1184 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
1185 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1186 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1187 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001188 {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich_dc},
Idwer Vollering326a0602011-06-18 18:45:41 +00001189 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1190 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1191 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1192 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1193 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
1194 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1195 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1196 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1197 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1198 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
1199 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
1200 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
1201 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1202 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
1203 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
1204 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1205 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
1206 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001207 {0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001208 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1209 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
1210 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1211 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001212 {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001213 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1214 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1215 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_ich10},
1216 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_ich10},
1217 {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_ich10},
1218 {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_ich10},
1219 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_ich10},
1220 {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_ich10},
1221 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_ich10},
1222 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_ich10},
1223 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
1224 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_ich10},
1225 {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_ich10},
1226 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_ich10},
1227 {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_ich10},
1228 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_ich10},
1229 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_ich10},
1230 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
1231 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1232 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1233 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Idwer Vollering570dcc742011-06-18 18:45:50 +00001234 {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
1235 {0x8086, 0x8186, NT, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_poulsbo},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001236#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001237 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001238};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001239
Uwe Hermanna7e05482007-05-09 10:17:44 +00001240int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001241{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001242 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001243 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001244 int i;
Stefan Tauner00155492011-06-26 20:45:35 +00001245 char *s;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001246
Uwe Hermann372eeb52007-12-04 21:49:06 +00001247 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001248 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1249 dev = pci_dev_find(chipset_enables[i].vendor_id,
1250 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001251 if (!dev)
1252 continue;
1253 if (ret != -2) {
1254 msg_pinfo("WARNING: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001255 "\"%s %s\"\n"
1256 "ignoring, please report lspci and board URL "
1257 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001258 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001259 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001260 chipset_enables[i].vendor_name,
1261 chipset_enables[i].device_name);
1262 continue;
1263 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001264 msg_pinfo("Found chipset \"%s %s\"",
1265 chipset_enables[i].vendor_name,
1266 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00001267 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001268 chipset_enables[i].vendor_id,
1269 chipset_enables[i].device_id);
Stefan Taunerec8c2482011-07-21 19:59:34 +00001270 msg_pinfo(". ");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001271
Stefan Taunerec8c2482011-07-21 19:59:34 +00001272 if (chipset_enables[i].status == NT) {
1273 msg_pinfo("\nThis chipset is marked as untested. If "
1274 "you are using an up-to-date version\nof "
1275 "flashrom please email a report to "
1276 "flashrom@flashrom.org including a\nverbose "
1277 "(-V) log. Thank you!\n");
1278 }
1279 msg_pinfo("Enabling flash write... ");
Uwe Hermann05fab752009-05-16 23:42:17 +00001280 ret = chipset_enables[i].doit(dev,
1281 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001282 if (ret == NOT_DONE_YET) {
1283 ret = -2;
1284 msg_pinfo("OK - searching further chips.\n");
1285 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001286 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001287 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001288 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001289 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00001290 msg_pinfo("PROBLEMS, continuing anyway\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001291 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001292
Stefan Tauner00155492011-06-26 20:45:35 +00001293 s = flashbuses_to_text(buses_supported);
1294 msg_pinfo("This chipset supports the following protocols: %s.\n", s);
1295 free(s);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001296
1297 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001298}