commit | eeef125b39cc7e19d987b5b40e92b7865dddd19a | [log] [tgz] |
---|---|---|
author | Edward O'Callaghan <quasisec@google.com> | Mon Nov 02 14:43:10 2020 +1100 |
committer | Edward O'Callaghan <quasisec@chromium.org> | Sat Nov 14 03:27:15 2020 +0000 |
tree | 581f8b8672bf20a3bcd925141b4e050948c5546d | |
parent | 1b4de5c600f333ef32706db8d2883642b078f8bd [diff] |
chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} support Modified to be pch7 over pch6 as per-coreboot and review comments. BUG=none BRANCH=none TEST=none Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>