Add support for the Open Graphics Project development card, OGD1, as a SPI flash programmer

The project is in the the process of designing and making a complete,
open source, graphics card. More info at http://wiki.opengraphics.org.

The first development card is a PCI add in card containing a couple of
FPGAs and a couple of serial flash chips (amongst other things). The
FPGAs are called XP10 and S3 (their part numbers). The XP10 contains its
own flash and does not need to be programmed by flashrom - it ensures
that the device can enumerate on the PCI bus without needing further
configuration.

The larger FPGA is the S3. This is configured from a large SPI flash
(2 MBytes). The second SPI flash is used to store the VGA BIOS. It is
smaller (128 KBytes). This patch adds support for programming either of
the two SPI flash chips.

The programmer device takes one configuration option which selects which
of the two flash chips is accessed. This must be set to either "cprom"
or "bprom". (The project refers to the two chips as "cprom" / "bprom",
"s3" and "bios" are more readable alternatives).

Add support for SST SST25VF010 (REMS). Mark SST SST25VF016B as tested
for write.

Corresponding to flashrom svn r1241.

Signed-off-by: Mark Marshall <mark.marshall@csr.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
diff --git a/ogp_spi.c b/ogp_spi.c
new file mode 100644
index 0000000..fb52a8c
--- /dev/null
+++ b/ogp_spi.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2010 Mark Marshall
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "flash.h"
+#include "programmer.h"
+
+#define PCI_VENDOR_ID_OGP 0x1227
+
+/* These are the register addresses for the OGD1 / OGA1.  If they are
+ * different for later versions of the hardware then we will need
+ * logic to select between the different hardware versions. */
+#define OGA1_XP10_BPROM_SI			     0x0040 /*	W */
+#define OGA1_XP10_BPROM_SO			     0x0040 /*	R */
+#define OGA1_XP10_BPROM_CE_BAR			     0x0044 /*	W */
+#define OGA1_XP10_BPROM_SCK			     0x0048 /*	W */
+#define OGA1_XP10_BPROM_REG_SEL			     0x004C /*	W */
+#define OGA1_XP10_CPROM_SI			     0x0050 /*	W */
+#define OGA1_XP10_CPROM_SO			     0x0050 /*	R */
+#define OGA1_XP10_CPROM_CE_BAR			     0x0054 /*	W */
+#define OGA1_XP10_CPROM_SCK			     0x0058 /*	W */
+#define OGA1_XP10_CPROM_REG_SEL			     0x005C /*	W */
+
+static uint8_t *ogp_spibar;
+
+static uint32_t ogp_reg_sel;
+static uint32_t ogp_reg_siso;
+static uint32_t ogp_reg__ce;
+static uint32_t ogp_reg_sck;
+
+const struct pcidev_status ogp_spi[] = {
+	{PCI_VENDOR_ID_OGP, 0x0000, OK, "Open Graphics Project", "Development Board OGD1"},
+	{},
+};
+
+static void ogp_request_spibus(void)
+{
+	pci_mmio_writel(1, ogp_spibar + ogp_reg_sel);
+}
+
+static void ogp_release_spibus(void)
+{
+	pci_mmio_writel(0, ogp_spibar + ogp_reg_sel);
+}
+
+static void ogp_bitbang_set_cs(int val)
+{
+	pci_mmio_writel(val, ogp_spibar + ogp_reg__ce);
+}
+
+static void ogp_bitbang_set_sck(int val)
+{
+	pci_mmio_writel(val, ogp_spibar + ogp_reg_sck);
+}
+
+static void ogp_bitbang_set_mosi(int val)
+{
+	pci_mmio_writel(val, ogp_spibar + ogp_reg_siso);
+}
+
+static int ogp_bitbang_get_miso(void)
+{
+	uint32_t tmp;
+
+	tmp = pci_mmio_readl(ogp_spibar + ogp_reg_siso);
+	return tmp & 0x1;
+}
+
+static const struct bitbang_spi_master bitbang_spi_master_ogp = {
+	.type = BITBANG_SPI_MASTER_OGP,
+	.set_cs = ogp_bitbang_set_cs,
+	.set_sck = ogp_bitbang_set_sck,
+	.set_mosi = ogp_bitbang_set_mosi,
+	.get_miso = ogp_bitbang_get_miso,
+	.request_bus = ogp_request_spibus,
+	.release_bus = ogp_release_spibus,
+};
+
+int ogp_spi_init(void)
+{
+	char *type;
+
+	type = extract_programmer_param("rom");
+
+	if (!type) {
+		msg_perr("Please use flashrom -p ogp_spi:rom=... to specify "
+			 "which flashchip you want to access.\n");
+		return 1;
+	} else if (!strcasecmp(type, "bprom") || !strcasecmp(type, "bios")) {
+		ogp_reg_sel  = OGA1_XP10_BPROM_REG_SEL;
+		ogp_reg_siso = OGA1_XP10_BPROM_SI;
+		ogp_reg__ce  = OGA1_XP10_BPROM_CE_BAR;
+		ogp_reg_sck  = OGA1_XP10_BPROM_SCK;
+	} else if (!strcasecmp(type, "cprom") || !strcasecmp(type, "s3")) {
+		ogp_reg_sel  = OGA1_XP10_CPROM_REG_SEL;
+		ogp_reg_siso = OGA1_XP10_CPROM_SI;
+		ogp_reg__ce  = OGA1_XP10_CPROM_CE_BAR;
+		ogp_reg_sck  = OGA1_XP10_CPROM_SCK;
+	} else {
+		msg_perr("Invalid or missing rom= parameter.\n");
+		return 1;
+	}
+
+	get_io_perms();
+
+	io_base_addr = pcidev_init(PCI_VENDOR_ID_OGP, PCI_BASE_ADDRESS_0,
+				   ogp_spi);
+
+	ogp_spibar = physmap("OGP registers", io_base_addr, 4096);
+
+	/* no delay for now. */
+	if (bitbang_spi_init(&bitbang_spi_master_ogp, 0))
+		return 1;
+
+	buses_supported = CHIP_BUSTYPE_SPI;
+	spi_controller = SPI_CONTROLLER_OGP;
+
+	return 0;
+}
+
+int ogp_spi_shutdown(void)
+{
+	physunmap(ogp_spibar, 4096);
+	pci_cleanup(pacc);
+	release_io_perms();
+
+	return 0;
+}