Remove delays in JEDEC erase sequence
It is extremely unlikely that a chip not requiring delays in probe does
require them in erase. We observed unreliable erasing with a SST49LF004A
with these delays, so remove them if the are not required.
In review, I got the hint that "probe_jedec goes further by making that
call conditional on nonzero delay". I decided to ignore that. For
internal_delay, the small amount of clock cycles wasted for calling
programmer_delay(0) is negligible compared to LPC cycle times. It might
be an issue for 5 wasted bytes on the serial line in serprog. OTOH,
flash erase is still slow compared to 6*5 bytes on a serial port at
Corresponding to flashrom svn r1288.
Signed-off-by: Michael Karcher <firstname.lastname@example.org>
Acked-by: Carl-Daniel Hailfinger <email@example.com>
1 file changed