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review.coreboot.org / coreboot / refs/heads/main / src / northbridge / intel / x4x / raminit_ddr23.c
  1. 4d06ff0 nb/intel/x4x: Use write32p and read32p by Arthur Heymans · 3 years ago
  2. 2aeb2a1 nb/intel/x4x: Prepare for x86_64 support by Arthur Heymans · 3 years ago
  3. 2bb361f nb/intel/x4x: Refactor sync DLL programming (part 2) by Nico Huber · 3 years, 3 months ago
  4. a20a02e nb/intel/x4x: Refactor sync DLL programming (part 1) by Nico Huber · 3 years, 3 months ago
  5. b6a2ebe nb/intel/x4x: Sort code in program_dll() by Nico Huber · 3 years, 3 months ago
  6. a5146f3 nb/intel/x4x: Use new fixed BAR accessors by Angel Pons · 3 years, 3 months ago
  7. 93aab51 nb/intel/x4x: Correct and use macros for CLKCFG by Angel Pons · 3 years, 3 months ago
  8. dd7ce4e nb/intel/x4x: Reflow long lines by Angel Pons · 3 years, 3 months ago
  9. c024c14 nb/intel/x4x: Correct sync DLL phase search by Angel Pons · 3 years, 3 months ago
  10. 06d224f nb/intel/x4x: Correct DDR3 turnaround table by Angel Pons · 3 years, 6 months ago
  11. b35adab nb/intel/x4x: Constify DDR2 ODT table by Angel Pons · 3 years, 6 months ago
  12. 7d3bd6b nb/intel/x4x: Clean up RCOMP cosmetics by Angel Pons · 3 years, 6 months ago
  13. a0b97f3 nb/intel/x4x: Drop unused first array index by Angel Pons · 3 years, 6 months ago
  14. 244391a nb/intel/x4x: Unroll programming RCOMP data group by Angel Pons · 3 years, 6 months ago
  15. 6b17794 nb/intel/x4x: Report if running in async mode by Angel Pons · 3 years, 6 months ago
  16. 43a5e0c nb/intel/x4x: Factor out setting Tx DLL tap and PI by Angel Pons · 3 years, 6 months ago
  17. 22fd0dc nb/intel/x4x: Correct ctrlset{2,3} register mask by Angel Pons · 3 years, 6 months ago
  18. 32f9bca nb/intel/x4x: Drop commented-out statement by Angel Pons · 3 years, 6 months ago
  19. 6538d91 northbridge/intel/x4x/raminit_ddr23.c: Remove repeated word by Elyes HAOUAS · 3 years, 6 months ago
  20. 9d20c84 nb/intel/x4x: Clean up raminit comments by Angel Pons · 3 years, 6 months ago
  21. 41e66ac nb/intel/x4x: Place raminit definitions in raminit.h by Angel Pons · 3 years, 10 months ago
  22. 2a8ceef nb/intel/x4x/iomap.h: Rename to memmap.h by Angel Pons · 3 years, 10 months ago
  23. dddd1cc src/northbridge: Drop unneeded empty lines by Elyes HAOUAS · 3 years, 11 months ago
  24. cf0f7ed nb/intel/x4x/raminit_ddr23.c: Remove dead assignment by Elyes HAOUAS · 4 years ago
  25. 5ba154a src: Use space after 'if', 'for' by Elyes HAOUAS · 4 years ago
  26. d1c590a nb/intel/x4x: Define and use `HOST_BRIDGE` macro by Angel Pons · 4 years ago
  27. 4a9569a nb/intel/x4x: Use PCI bitwise ops by Angel Pons · 4 years, 1 month ago
  28. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 2 months ago
  29. ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 2 months ago
  30. 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 2 months ago
  31. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  32. ef90609 src: capitalize 'RAM' by Elyes HAOUAS · 4 years, 5 months ago
  33. 68ec3eb src: Move 'static' to the beginning of declaration by Elyes HAOUAS · 5 years ago
  34. 8bb2bac nb/intel/x4x/raminit: Move dummy reads after JEDEC init by Arthur Heymans · 5 years ago
  35. 5033d6c nb/intel/x4x: Die on invalid memory speeds by Jacob Garber · 5 years ago
  36. e951e8e nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} by Elyes HAOUAS · 5 years ago
  37. c53665c nb/intel/x4x: Remove variable set but not used by Elyes HAOUAS · 5 years ago
  38. cd49cce coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) by Julius Werner · 5 years ago
  39. 13f6650 device/mmio.h: Add include file for MMIO ops by Kyösti Mälkki · 5 years ago
  40. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  41. 586f24d northbridge: Remove unneeded include <pc80/mc146818rtc.h> by Elyes HAOUAS · 6 years ago
  42. 0ce41f1 src: Add required space after "switch" by Elyes HAOUAS · 6 years ago
  43. d2b9ec1 src: Remove unneeded include "{arch,cpu}/cpu.h" by Elyes HAOUAS · 6 years ago
  44. d522db0 nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware by Arthur Heymans · 6 years ago
  45. 3a2f900 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] by Felix Held · 6 years ago
  46. 432575c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] by Felix Held · 6 years ago
  47. 7345a17 nb/intel/x4x: Fix a few things in set_enhanced_mode by Arthur Heymans · 6 years ago
  48. 0602ce6 nb/intel/x4x: Add the option for stacked channel map settings by Arthur Heymans · 6 years ago
  49. 0d28495 nb/intel/x4x: Adapt post JEDEC for DDR3 by Arthur Heymans · 7 years ago
  50. 3fa103a nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings by Arthur Heymans · 7 years ago
  51. b4a7804 nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings by Arthur Heymans · 7 years ago
  52. b5170c3 nb/intel/x4x: Implement write leveling by Arthur Heymans · 7 years ago
  53. f128726 nb/intel/x4x: Add DDR3 JEDEC init by Arthur Heymans · 7 years ago
  54. e6cc21e nb/intel/x4x/raminit: DDR3 specific ODT by Arthur Heymans · 7 years ago
  55. 0d1c9b0 nb/intel/x4x: Add DDR3 rcomp by Arthur Heymans · 7 years ago
  56. 638240e nb/intel/x4x/raminit: Support programming initials DD3 DLL setting by Arthur Heymans · 7 years ago
  57. 66a0f55 nb/intel/x4x/raminit: Support programming DDR3 timings by Arthur Heymans · 7 years ago
  58. 7a3a319 nb/intel/x4x/raminit: Make programming launch ddr3 specific by Arthur Heymans · 7 years ago
  59. 840c27e nb/intel/x4x/raminit: Make programming crossclock support DDR3 by Arthur Heymans · 7 years ago
  60. a2cc231 nb/intel/x4x: Rename a things that are not specific to DDR2 by Arthur Heymans · 7 years ago[Renamed (97%) from src/northbridge/intel/x4x/raminit_ddr2.c]
  61. 701da39 nb/intel/x4x/raminit: Fix programming dual channel registers by Arthur Heymans · 7 years ago
  62. 16a70a4 nb/intel/x4x: Change memory layout to improve MTRR by Arthur Heymans · 7 years ago
  63. dfce932 nb/intel/x4x: Fix programming CxDRB by Arthur Heymans · 7 years ago
  64. 95c48cb nb/intel/x4x: Implement both read and write training by Arthur Heymans · 7 years ago
  65. 276049f nb/intel/x4x: Add a convenient macro to loop over bytelanes by Arthur Heymans · 7 years ago
  66. 1994e448 nb/intel/x4x: Clarify the raminit memory mapping by Arthur Heymans · 7 years ago
  67. 0bf87de nb/intel/x4x: Refactor setting default dll settings by Arthur Heymans · 7 years ago
  68. adc571a nb/intel/x4x: Use SPI flash to cache raminit results by Arthur Heymans · 7 years ago
  69. 7be74db nb/x4x/raminit_ddr2: Refactor clock configuration slightly by Jonathan Neuschäfer · 6 years ago
  70. 3cf9403 nb/x4x/raminit: Rewrite SPD decode and timing selection by Arthur Heymans · 7 years ago
  71. 24798a1 nb/intel/x4x: Fix booting with FSB800 DDR667 combination by Arthur Heymans · 7 years ago
  72. 6d7a8c1 nb/intel/x4x/raminit: Rework receive enable calibration by Arthur Heymans · 7 years ago
  73. 3876f24 nb/intel/x4x: Rework programming DQ and DQS DLL timings by Arthur Heymans · 7 years ago
  74. 349e085 sb/intel/i82801jx: Add correct PCI ids and change names by Arthur Heymans · 7 years ago
  75. 37689fa nb/intel/x4x/raminit: Initialise async variable by Arthur Heymans · 7 years ago
  76. 27f0ca1 nb/intel/x4x: Use a struct for dll settings instead of an array by Arthur Heymans · 7 years ago
  77. cfa2eaa nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP by Arthur Heymans · 7 years ago
  78. e729366 nb/intel/x4x/raminit: Remove very long delay by Arthur Heymans · 7 years ago
  79. ddc8828 nb/x4x/raminit.c: Remove ME locking code by Arthur Heymans · 7 years ago
  80. bb5e77c nb/x4x: Move checkreset before SPD reading by Arthur Heymans · 8 years ago
  81. 70a1dda nb/intel/x4x: Fix issues found by checkpatch.pl by Arthur Heymans · 7 years ago
  82. ef7e98a nb/intel/x4x: Implement resume from S3 suspend by Arthur Heymans · 8 years ago
  83. 97e13d8 nb/intel/x4x: Fix raminit on reset path by Arthur Heymans · 8 years ago
  84. eee4f6b nb/x4x/raminit: Fix programming dram timings by Arthur Heymans · 8 years ago
  85. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  86. 8a3514d nb/x4x/raminit.c: Improve crossclock table cosmetics by Arthur Heymans · 8 years ago
  87. 523e90f nb/intel/x4x: Increase MMIO PCI space to 2GiB by Damien Zammit · 8 years ago
  88. 12df950 northbridge/intel: Add required space before opening parenthesis '(' by Elyes HAOUAS · 8 years ago
  89. 27f94ee x4x: add non documented vram sizes by Arthur Heymans · 8 years ago
  90. 7c2e539 nb/intel/x4x: Fix CAS latency detection and max memory detection by Damien Zammit · 8 years ago
  91. 68e1dcf nb/intel/x4x: Fix unpopulated value by Damien Zammit · 8 years ago
  92. d63115d nb/intel/x4x: Tidy up raminit and fix msbpos() function by Damien Zammit · 8 years ago
  93. 9fb08f5 nb/intel/x4x: Fix memory hole with both channels populated by Damien Zammit · 8 years ago
  94. cbe3892 northbridge/intel/x4x: clean up includes by Martin Roth · 9 years ago
  95. 4b513a6 northbridge/intel/x4x: Native raminit by Damien Zammit · 9 years ago