Gitiles
Code Review Sign In
review.coreboot.org / coreboot / refs/heads/main / src / northbridge / intel / x4x / Makefile.mk
  1. 8b1aa38 northbridge: Rename Makefiles from .inc to .mk by Martin Roth · 6 months ago[Renamed from src/northbridge/intel/x4x/Makefile.inc]
  2. c4b7027 src: Remove leading blank lines from SPDX header by Elyes HAOUAS · 4 years, 2 months ago
  3. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 2 months ago
  4. c49d7a3 src/: Replace GPL boilerplate with SPDX headers by Patrick Georgi · 4 years, 2 months ago
  5. f3f36fa src (minus soc and mainboard): Remove copyright notices by Patrick Georgi · 4 years, 4 months ago
  6. 7843bd5 nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK by Arthur Heymans · 4 years, 8 months ago
  7. bf53acc nb/intel/x4x: Move boilerplate romstage to a common location by Arthur Heymans · 4 years, 8 months ago
  8. fe481eb northbridge/intel: Rename ram_calc.c to memmap.c by Kyösti Mälkki · 5 years ago
  9. aba8fb1 intel/i945,gm45,pineview,x4x: Move stage cache support function by Kyösti Mälkki · 5 years ago
  10. a402a9e nb/intel/x4x: Put stage cache in TSEG by Arthur Heymans · 6 years ago
  11. 4ff675e nb/intel/x4x: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  12. a2cc231 nb/intel/x4x: Rename a things that are not specific to DDR2 by Arthur Heymans · 7 years ago
  13. 95c48cb nb/intel/x4x: Implement both read and write training by Arthur Heymans · 7 years ago
  14. 0bf87de nb/intel/x4x: Refactor setting default dll settings by Arthur Heymans · 7 years ago
  15. 6d7a8c1 nb/intel/x4x/raminit: Rework receive enable calibration by Arthur Heymans · 7 years ago
  16. ef7e98a nb/intel/x4x: Implement resume from S3 suspend by Arthur Heymans · 8 years ago
  17. a090ae0 nb/intel/x4x: Add DMI/EP init by Damien Zammit · 8 years ago
  18. 4b513a6 northbridge/intel/x4x: Native raminit by Damien Zammit · 9 years ago
  19. 43a1f78 northbridge/intel/x4x: Intel 4-series northbridge support by Damien Zammit · 9 years ago