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coreboot
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fd98c65b9d89e1ca665e25b6abf6d2019855e85a
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src
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southbridge
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intel
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bd82x6x
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finalize.c
fd98c65
intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
by Kyösti Mälkki
· 11 years ago
54d6abd
Drop some duplicates of PCI-e config functions
by Kyösti Mälkki
· 11 years ago
d1fb564
sandybridge: Add option to lock SPI regions on resume
by Nico Huber
· 11 years ago
24d1d4b
x86: Unify arch/io.h and arch/romcc_io.h
by Stefan Reinauer
· 11 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 11 years ago
600784e
spi.h: Rename the spi.h to spi-generic.h
by Zheng Bao
· 12 years ago
04c5bae
Define post codes for OS boot and resume
by Duncan Laurie
· 12 years ago
312ee0c
SPI: re-init SMM SPI driver after lockdown
by Duncan Laurie
· 12 years ago
f1c76ef
ELOG: Don't disable SPI controller lockdown
by Duncan Laurie
· 12 years ago
54cba3b
SMM: Skip locking SPI registers in finalize step
by Duncan Laurie
· 12 years ago
8e07382
Add support for Intel Panther Point PCH
by Stefan Reinauer
· 12 years ago