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review.coreboot.org / coreboot / f5b09dbe1840e2ba2bbc9b2c6225e838cb7a32b9 / src / soc / amd / mendocino / chipset_mendocino.cb
  1. f5b09db soc/amd/*/chipset.cb: don't call dummy device functions host bridges by Felix Held · 7 months ago
  2. ed6c999 soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree by Felix Held · 1 year, 1 month ago
  3. faa9fb6 soc/amd/mendocino: drop code for non-existing eMMC controller by Felix Held · 1 year, 3 months ago
  4. c9ce5f6 soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off by Martin Roth · 1 year, 3 months ago
  5. e32565c soc/amd/mendocino: Remove GPP bridge to Bus B by Martin Roth · 1 year, 4 months ago
  6. ed029a9 soc/amd/mendocino: Remove 2 unused PCIe functions by Martin Roth · 1 year, 4 months ago
  7. 8f2e5c9 soc/amd: introduce and use common amd_cpu_bus_ops struct by Felix Held · 1 year, 6 months ago
  8. aab7f04 soc/amd/*/data_fabric: Use common device ops by Fred Reitberger · 1 year, 8 months ago
  9. 97e6125 soc/amd/*/uart: commonize UART code and MMIO device driver by Felix Held · 1 year, 9 months ago
  10. b3dcb96 soc/amd/*: Hook up IOMMU ops in devicetree by Arthur Heymans · 1 year, 9 months ago
  11. c6f029c soc/amd/*: Hook up LPC ops in devicetree by Arthur Heymans · 1 year, 9 months ago
  12. fd2bb9b soc/amd/*: Hook up SMBus ops to devicetree by Arthur Heymans · 1 year, 9 months ago
  13. 65d73cc soc/amd: factor out common eMMC code by Felix Held · 1 year, 9 months ago
  14. 796a8f3 soc/amd/*: Hook up GPU ops in devicetree by Arthur Heymans · 1 year, 9 months ago
  15. b171f76 soc/amd/*: Hook up GPP bridges ops to devicetree by Arthur Heymans · 1 year, 9 months ago
  16. 987ec88 soc/amd/acp: Hook up ops in devicetree by Arthur Heymans · 1 year, 9 months ago
  17. 6a5d770 soc/amd/mendocino: Use devicetree ops over pci driver by Arthur Heymans · 1 year, 9 months ago
  18. 7f38077 soc/amd/*: Hook up device_operations in chipset.cb by Arthur Heymans · 1 year, 10 months ago
  19. 4f73242 treewide: Rename Sabrina to Mendocino by Jon Murphy · 2 years ago[Renamed (98%) from src/soc/amd/sabrina/chipset_sabrina.cb]
  20. d3dae3d soc/amd/sabrina: Add support for Rembrandt SoC as base SoC by Ritul Guru · 2 years, 3 months ago[Renamed from src/soc/amd/sabrina/chipset.cb]
  21. 6e368f7 soc/amd/sabrina: Add XHCI configuration by Jon Murphy · 2 years, 5 months ago
  22. a3f8eda soc/amd/sabrina/chipset.cb: update USB ports by Felix Held · 2 years, 6 months ago
  23. 1c3b2a7 soc/amd/sabrina: update PCI devices in devicetree.cb by Felix Held · 2 years, 6 months ago
  24. b1fe9de soc/amd/sabrina: add additional UART controllers by Felix Held · 2 years, 6 months ago
  25. 3c44c62 soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne by Felix Held · 2 years, 6 months ago