Gitiles
Code Review Sign In
review.coreboot.org / coreboot / f1b58b78351d7ed220673e688a2f7bc9e96da4e2 / src / soc / intel / braswell / lpe.c
  1. f1b58b7 device/pci: Fix PCI accessor headers by Kyösti Mälkki · 5 years ago
  2. a342f39 src: Remove unneeded whitespace by Elyes HAOUAS · 6 years ago
  3. b13fac3 soc/intel/braswell: Get rid of device_t by Elyes HAOUAS · 6 years ago
  4. 5d6ab45 soc/intel/braswell: add resource allocation for LPE BAR1 by Matt DeVillier · 7 years ago
  5. 83ef07a soc/intel/braswell: increase LPEA fw allocation to 2MiB by Matt DeVillier · 7 years ago
  6. d94cff6 soc/intel/braswell: Fix most of the issues detected by checkpatch by Lee Leahy · 7 years ago
  7. 1072e7d soc/intel/braswell: Add int to unsigned by Lee Leahy · 7 years ago
  8. aff502e soc/braswell: Fix DSP clock by fdurairx · 9 years ago
  9. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  10. 3247172 Braswell: Add Braswell SOC support by Lee Leahy · 9 years ago
  11. 25509ee Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  12. 77ff0b1 Braswell: Use Baytrail as Comparison Base by Lee Leahy · 9 years ago