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review.coreboot.org / coreboot / e9665959edeba6ae2d5364c4f7339704b6b6fd42 / src / soc / intel / alderlake / romstage / fsp_params.c
  1. e966595 treewide: Remove "ERROR: "/"WARN: " prefixes from log messages by Julius Werner · 2 years, 6 months ago
  2. ff553ba soc/intel/alderlake: Check clkreq overlap by Kane Chen · 2 years, 7 months ago
  3. b4a169a soc/intel/alderlake: Add option to make MRC log silent by Subrata Banik · 2 years, 7 months ago
  4. 461ff1d soc/intel: Move enum pcie_rp_type to intelblocks/pcie_rp.h by Tim Wawrzynczak · 2 years, 7 months ago
  5. fc69b9d soc/intel/alderlake: Add the CnviDdrRfim configuration by Ronak Kanabar · 2 years, 9 months ago
  6. 3b03798 soc/intel/alderlake: Disable VT-d for early silicons by Meera Ravindranath · 2 years, 8 months ago
  7. 9a7fbbc soc/intel/adl: Skip sending MBP HOB to save boot time by MAULIK V VAGHELA · 2 years, 9 months ago
  8. 8fcefd3 soc/intel/alderlake: add MaxDramSpeed config by Casper Chang · 2 years, 10 months ago
  9. 87685c5 soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h' by Subrata Banik · 3 years ago
  10. 7b8d11b soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDs by Subrata Banik · 3 years ago
  11. 0007fa9 soc/intel/alderlake: Update mainboard_memory_init_params() argument by Subrata Banik · 3 years, 1 month ago
  12. 85c9dda soc/intel/alderlake/romstage: Refactor soc_memory_init_params function by Subrata Banik · 3 years, 1 month ago
  13. 8a18bd8 soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx by Subrata Banik · 3 years, 1 month ago
  14. 50134ec soc/intel/alderlake: Make use of is_devfn_enabled() function by Subrata Banik · 3 years, 1 month ago
  15. 930b643 soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask` by Subrata Banik · 3 years, 1 month ago
  16. 24b1c54 soc/intel/alderlake: Set SaIpuEnable UPD according to devicetree by Tim Wawrzynczak · 3 years, 1 month ago
  17. d047927 soc/intel/alderlake: Set Base Addresses for TBT DMA remapping engines by Sridhar Siricilla · 3 years, 2 months ago
  18. cea4f92 soc/intel/alderlake: Add CrashLog implementation for Intel ADL by Francois Toguo · 3 years, 3 months ago
  19. a3f7deb soc/intel/alderlake: Fill FSPM UPDs for VT-d configuration by Meera Ravindranath · 3 years, 4 months ago
  20. 50f8b4e soc/intel/alderlake: Add enum for HDA audio configuration by Sugnan Prabhu S · 3 years, 4 months ago
  21. c1c1ba5 soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h by Furquan Shaikh · 3 years, 3 months ago
  22. 5b302b2 soc/intel/alderlake: Refactor PCIE port config by Eric Lai · 3 years, 7 months ago
  23. d74cd60 soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD by Subrata Banik · 3 years, 6 months ago
  24. 85144d9 soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs by Subrata Banik · 3 years, 6 months ago
  25. 407488e src/soc/intel/alderlake: Enable the PCH HDA by V Sowmya · 3 years, 7 months ago
  26. 28371e2 soc/intel/alderlake/romstage: Skip GPIO configuration from FSP by Subrata Banik · 3 years, 9 months ago
  27. 0aed4e5 soc/intel/alderlake: Enable TME for Alder Lake by Subrata Banik · 3 years, 9 months ago
  28. 2871e0e soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage by Subrata Banik · 3 years, 10 months ago
  29. 80835a1 soc/intel/alderlake/romstage: Fix compilation issue by Subrata Banik · 3 years, 10 months ago
  30. 292afef soc/intel/alderlake/romstage: Do initial SoC commit till romstage by Subrata Banik · 3 years, 10 months ago