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review.coreboot.org / coreboot / dd96ab698757c6b6f05612d92f38088e8f7069e5 / src / mainboard / intel / wtm2 / devicetree.cb
  1. dd96ab6 cpu/intel/haswell: Move chip_ops to cpu cluster by Arthur Heymans · 2 years, 8 months ago
  2. 4c4bd3c soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree by Arthur Heymans · 1 year, 8 months ago
  3. b7fe448 mb/intel/wtm2: Use Haswell CPU code by Angel Pons · 3 years, 9 months ago
  4. 3cc2c38 soc/intel/broadwell: Separate PCH in devicetree by Angel Pons · 3 years, 9 months ago
  5. 5e60637 mb/intel/wtm2: Prepare devicetree for PCH split by Angel Pons · 3 years, 9 months ago
  6. 4a6c0a3 broadwell: Factor out PIRQ routing from devicetree by Angel Pons · 4 years ago
  7. 4276050 mb/*/*/devicetree.cb: Normalize disabled PIRQ values by Angel Pons · 4 years ago
  8. 026fd87 mb/intel/wtm2/devicetree.cb: Align comments by Angel Pons · 4 years, 7 months ago
  9. 0aa06cb wtm2: Convert to use soc/intel/broadwell by Duncan Laurie · 10 years ago
  10. 0e93915 wtm2: Set SerialIO I2C ports to 3.3V by Duncan Laurie · 11 years ago
  11. 7c35131 haswell: configure c-states by Aaron Durbin · 11 years ago
  12. 9591210 wtm2: Enable SerialIO devices in ACPI mode by Duncan Laurie · 11 years ago
  13. 467f31d haswell/lynxpoint: Use new PCH/PM helper functions by Duncan Laurie · 11 years ago
  14. afad056 Add Intel Whitetip Mountain 2 mainboard by Duncan Laurie · 12 years ago