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review.coreboot.org / coreboot / dabebc3716bac1dbe9445dfb2bbbbb833ee21de1 / src / northbridge / intel / sandybridge / raminit_ivy.c
  1. dabebc3 nb/intel/sandybridge: support more XMP timings by Dan Elkouby · 6 years ago
  2. 9ed74b5 nb/intel/ivybridge: Improve CAS freq selection by Arthur Heymans · 7 years ago
  3. cb7d6a1 nb/intel/sandybridge/raminit: Add default values by Patrick Rudolph · 8 years ago
  4. cab4d3d nb/intel/sandybridge/raminit: Add 100MHz refclock support by Patrick Rudolph · 8 years ago
  5. 77eaba3 nb/intel/sandybridge/raminit: Use Ivy Bridge specific values by Patrick Rudolph · 8 years ago
  6. 50db9c9 nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings by Arthur Heymans · 7 years ago
  7. 305035c nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge by Patrick Rudolph · 8 years ago