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review.coreboot.org / coreboot / d522db048b1e1b6e61f585859d7a95b308cb53de / src / northbridge / intel / x4x
  1. d522db0 nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware by Arthur Heymans · 6 years ago
  2. 17ad459 nb/intel/*: Account for cbmem_top alignment by Arthur Heymans · 6 years ago
  3. a342f39 src: Remove unneeded whitespace by Elyes HAOUAS · 6 years ago
  4. b1ba662 nb/intel/x4x: Fix P45 CAPID max frequency by Arthur Heymans · 6 years ago
  5. 8ddd7d1 nb/intel/x4x: Program read training results to all ranks by Arthur Heymans · 6 years ago
  6. 88607a4 src: Use tabs for indentation by Elyes HAOUAS · 6 years ago
  7. b0c6cff nb/intel/x4x: Don't use cached settings if CPU FSB has been changed by Arthur Heymans · 6 years ago
  8. 3e3bae0 nb/intel/x4x/gma.c: fix skipping of native graphics init by Stefan Tauner · 6 years ago
  9. e6c8f7e nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled by Arthur Heymans · 6 years ago
  10. 3d45000 src: Fix typo by Elyes HAOUAS · 6 years ago
  11. 64f6b71 src/northbridge: Fix typo by Elyes HAOUAS · 6 years ago
  12. 3a2f900 x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] by Felix Held · 6 years ago
  13. c6e13b6 nb/intel/x4x: Don't use PCI operations on the pci_domain device by Arthur Heymans · 6 years ago
  14. 432575c x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] by Felix Held · 6 years ago
  15. 6cd2c2f northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros by Felix Held · 6 years ago
  16. a8a9f34 sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables by Arthur Heymans · 7 years ago
  17. df946b8 nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset by Arthur Heymans · 6 years ago
  18. e809305 nb/intel/x4x: Deprecate native graphic init by Arthur Heymans · 6 years ago
  19. 7345a17 nb/intel/x4x: Fix a few things in set_enhanced_mode by Arthur Heymans · 6 years ago
  20. 5a9dbde nb/intel/x4x: Work around a quirk by Arthur Heymans · 6 years ago
  21. 0602ce6 nb/intel/x4x: Add the option for stacked channel map settings by Arthur Heymans · 6 years ago
  22. f2dd049 libgfxinit: Enable G45 support (for GM45/X4X) by Nico Huber · 7 years ago
  23. 730df3c arch/x86: Make RELOCATABLE_RAMSTAGE the default by Kyösti Mälkki · 8 years ago
  24. 4ff675e nb/intel/x4x: Switch to POSTCAR_STAGE by Arthur Heymans · 6 years ago
  25. 089b908 nb/intel: Use postcar_frame_add_romcache() by Nico Huber · 6 years ago
  26. f369e60 northbridge/intel: Remove unneeded includes by Elyes HAOUAS · 6 years ago
  27. 654cc2f {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate by Nico Huber · 6 years ago
  28. 0d28495 nb/intel/x4x: Adapt post JEDEC for DDR3 by Arthur Heymans · 7 years ago
  29. 3fa103a nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings by Arthur Heymans · 7 years ago
  30. b4a7804 nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings by Arthur Heymans · 7 years ago
  31. b5170c3 nb/intel/x4x: Implement write leveling by Arthur Heymans · 7 years ago
  32. f128726 nb/intel/x4x: Add DDR3 JEDEC init by Arthur Heymans · 7 years ago
  33. e6cc21e nb/intel/x4x/raminit: DDR3 specific ODT by Arthur Heymans · 7 years ago
  34. 0d1c9b0 nb/intel/x4x: Add DDR3 rcomp by Arthur Heymans · 7 years ago
  35. 638240e nb/intel/x4x/raminit: Support programming initials DD3 DLL setting by Arthur Heymans · 7 years ago
  36. 66a0f55 nb/intel/x4x/raminit: Support programming DDR3 timings by Arthur Heymans · 7 years ago
  37. 7a3a319 nb/intel/x4x/raminit: Make programming launch ddr3 specific by Arthur Heymans · 7 years ago
  38. 840c27e nb/intel/x4x/raminit: Make programming crossclock support DDR3 by Arthur Heymans · 7 years ago
  39. a2cc231 nb/intel/x4x: Rename a things that are not specific to DDR2 by Arthur Heymans · 7 years ago
  40. 1848ba3 nb/x4x/raminit: Decode ddr3 dimms by Arthur Heymans · 7 years ago
  41. 701da39 nb/intel/x4x/raminit: Fix programming dual channel registers by Arthur Heymans · 7 years ago
  42. 3de3031 {mb,nb,soc}: Remove references to pci_bus_default_ops() by Nico Huber · 6 years ago
  43. 16a70a4 nb/intel/x4x: Change memory layout to improve MTRR by Arthur Heymans · 7 years ago
  44. dfce932 nb/intel/x4x: Fix programming CxDRB by Arthur Heymans · 7 years ago
  45. 95c48cb nb/intel/x4x: Implement both read and write training by Arthur Heymans · 7 years ago
  46. fea02e1 nb/x4x: Get rid of device_t by Elyes HAOUAS · 7 years ago
  47. d4e5762 nb/intel/x4x: Fix computing page_size by Arthur Heymans · 7 years ago
  48. a4e8f67b nb/intel/x4x/rcven.c: Change the verbosity of some messages by Arthur Heymans · 7 years ago
  49. 276049f nb/intel/x4x: Add a convenient macro to loop over bytelanes by Arthur Heymans · 7 years ago
  50. 1994e448 nb/intel/x4x: Clarify the raminit memory mapping by Arthur Heymans · 7 years ago
  51. 0bf87de nb/intel/x4x: Refactor setting default dll settings by Arthur Heymans · 7 years ago
  52. adc571a nb/intel/x4x: Use SPI flash to cache raminit results by Arthur Heymans · 7 years ago
  53. fc31e44 device/ddr2,ddr3: Rename and move a few things by Arthur Heymans · 7 years ago
  54. 7be74db nb/x4x/raminit_ddr2: Refactor clock configuration slightly by Jonathan Neuschäfer · 7 years ago
  55. d6f3dd8 nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout by Arthur Heymans · 7 years ago
  56. 3cf9403 nb/x4x/raminit: Rewrite SPD decode and timing selection by Arthur Heymans · 7 years ago
  57. f6f4ba9 nb/intel/x4x/rcven.c: Fix programming coarse offset by Arthur Heymans · 7 years ago
  58. f6aa7d9 nb/intel/*/gma: Port ACPI opregion to older platforms by Patrick Rudolph · 7 years ago
  59. 524d497 nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER by Arthur Heymans · 7 years ago
  60. 24798a1 nb/intel/x4x: Fix booting with FSB800 DDR667 combination by Arthur Heymans · 7 years ago
  61. 6d7a8c1 nb/intel/x4x/raminit: Rework receive enable calibration by Arthur Heymans · 7 years ago
  62. c3cbe94 nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I ports by Arthur Heymans · 7 years ago
  63. 8da2286 nb/intel/*/gma.c: Use macros for GMBUS numbers by Arthur Heymans · 7 years ago
  64. 3876f24 nb/intel/x4x: Rework programming DQ and DQS DLL timings by Arthur Heymans · 7 years ago
  65. 349e085 sb/intel/i82801jx: Add correct PCI ids and change names by Arthur Heymans · 7 years ago
  66. 6d8266b Kconfig: Add choice of framebuffer mode by Nico Huber · 7 years ago
  67. 7971582e Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFER by Nico Huber · 7 years ago
  68. ce642f0 Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG by Nico Huber · 7 years ago
  69. 37689fa nb/intel/x4x/raminit: Initialise async variable by Arthur Heymans · 7 years ago
  70. 27f0ca1 nb/intel/x4x: Use a struct for dll settings instead of an array by Arthur Heymans · 7 years ago
  71. cfa2eaa nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUP by Arthur Heymans · 7 years ago
  72. e729366 nb/intel/x4x/raminit: Remove very long delay by Arthur Heymans · 7 years ago
  73. cfd433b nb/intel/x4x: Fix uninitialized variable issue by Nico Huber · 7 years ago
  74. 512a2d1 nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESS by Arthur Heymans · 7 years ago
  75. 293445a nb/intel/x4x: Add support for second PEG slot by Arthur Heymans · 7 years ago
  76. 5e3cb72 nb/x4x: Do not enable IGD when not supported by Arthur Heymans · 7 years ago
  77. 2e7efe6 nb/intel/x4x: Don't run NGI if IGD has not been assigned VGA cycles by Arthur Heymans · 7 years ago
  78. c80748c nb/x4x: Add ramstage IGD disable function by Arthur Heymans · 7 years ago
  79. 4c4f56a nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically by Arthur Heymans · 7 years ago
  80. ddc8828 nb/x4x/raminit.c: Remove ME locking code by Arthur Heymans · 7 years ago
  81. 8565c03 nb/intel/x4x/raminit: Change reset type on incomplete raminit reset by Arthur Heymans · 7 years ago
  82. 4bc9c28 nb/intel/x4x/Kconfig: Don't fix CBFS_SIZE on i82801gx southbridge by Arthur Heymans · 7 years ago
  83. bb5e77c nb/x4x: Move checkreset before SPD reading by Arthur Heymans · 8 years ago
  84. 70a1dda nb/intel/x4x: Fix issues found by checkpatch.pl by Arthur Heymans · 7 years ago
  85. ef7e98a nb/intel/x4x: Implement resume from S3 suspend by Arthur Heymans · 8 years ago
  86. 97e13d8 nb/intel/x4x: Fix raminit on reset path by Arthur Heymans · 8 years ago
  87. eee4f6b nb/x4x/raminit: Fix programming dram timings by Arthur Heymans · 8 years ago
  88. 6d0c65e nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> by Arthur Heymans · 8 years ago
  89. 9e70ce0 nb/x4x: Add other Eaglelake IGD PCI DID to list by Arthur Heymans · 8 years ago
  90. 122e5bc intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGE by Kyösti Mälkki · 8 years ago
  91. 823020d intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup by Kyösti Mälkki · 8 years ago
  92. 811932a intel i945 gm45 x4x: Apply cbmem_top() alignment by Kyösti Mälkki · 8 years ago
  93. 530f677 buildsystem: Drop explicit (k)config.h includes by Kyösti Mälkki · 8 years ago
  94. 3d15e10 MMCONF_SUPPORT: Flip default to enabled by Kyösti Mälkki · 8 years ago
  95. 5b30b82 nb/x4x: Fix sticky scratchpad register offset by Arthur Heymans · 8 years ago
  96. 3c20906 nb/intel/x4x/raminit: Fix DIMM_IN_CHANNEL calculation by Nico Huber · 8 years ago
  97. 696abfc nb/intel/x4x: Fix and deflate `dimm_config` in raminit by Nico Huber · 8 years ago
  98. bac0fad Remove explicit select MMCONF_SUPPORT by Kyösti Mälkki · 8 years ago
  99. 128c104 nb/intel: Fix some spelling mistakes in comments and strings by Martin Roth · 8 years ago
  100. a4ffe9d intel post-car: Separate files for setup_stack_and_mtrrs() by Kyösti Mälkki · 8 years ago