1. 83a965d Implement GPIO configuration routines for the Intel 3100 southbridge, by Ed Swierk · 16 years ago
  2. 9d9518f cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a by Marc Jones · 16 years ago
  3. a9a5f49 By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 by Ed Swierk · 16 years ago
  4. c4a4116 by Ward Vandewege · 16 years ago
  5. 0dc5697 This patch halts the tco timer early in the boot process on all ICH series southbridges. by Joseph Smith · 16 years ago
  6. 2b85b63 Setting an integrated southbridge device (like SATA or USB2.0) to by Ed Swierk · 16 years ago
  7. 23cd49a Remove i82801DB files that I meant to delete in r3206. by Joseph Smith · 16 years ago
  8. 06ae639 Tiny style fix for consistency (trivial). by Ed Swierk · 16 years ago
  9. 868de98 Removal of i82801DB (ICH4) by Joseph Smith · 16 years ago
  10. c4e052c The early init code of several Intel southbridge chipsets calls by Ed Swierk · 16 years ago
  11. 71f846c Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots by Ed Swierk · 16 years ago
  12. 9c2255c Now coreboot performs IRQ routing for some boards. by Nikolay Petukhov · 16 years ago
  13. 316e07f Following patch adds K8M890 support. It initializes the AGP and graphics UMA. by Rudolf Marek · 16 years ago
  14. c221349 Following patch will setup KT890 HT automatically. It will find the by Rudolf Marek · 16 years ago
  15. aaea11b Here is an updated patch addressing most of Uwe's and Peter's by Ed Swierk · 16 years ago
  16. 5671787 Following patch extends the ROM decoding to last 1MB, allowing to use larger by Rudolf Marek · 16 years ago
  17. dd52e17 Following patch fixes the retrain/reset sequence which caused problem with some by Rudolf Marek · 16 years ago
  18. 8684520b This trivial patch removes an unused local variable, thus getting rid of by Ronald Hoogenboom · 16 years ago
  19. f327d9f Route device IRQ through PCI bridge instead in mptable. by Yinghai Lu · 16 years ago
  20. f8ee180 Rename almost all occurences of LinuxBIOS to coreboot. by Stefan Reinauer · 16 years ago
  21. 7e61e45 Please bear with me - another rename checkin. This qualifies as trivial, no by Stefan Reinauer · 16 years ago
  22. 0da5cde Additional early AMD8111 southbridge support for Barcelona platforms. by Marc Jones · 16 years ago
  23. 9da69f8 Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s): by Uwe Hermann · 16 years ago
  24. 447aafe Restructure/rename/comment a few 82371XX-related PCI IDs (trivial). by Uwe Hermann · 16 years ago
  25. c8cf4ad 1. Fix pirq routing table setting for GA-2761GXDK. by Morgan Tsai · 17 years ago
  26. 70ab323 Various cosmetic fixes and improvements (trivial). by Uwe Hermann · 17 years ago
  27. 31e805d * Maintaining SiS south bridge device IDs. * Strip unnecessary driver modules. by Morgan Tsai · 17 years ago
  28. cc3ccdb Add support for FID/VID changes messages. by Rudolf Marek · 17 years ago
  29. a6ddf25 Fine-tune the V-link bus between K8T890 and VT8237R and set by Rudolf Marek · 17 years ago
  30. cce5040 Add initial support for all known ICH* southbridges to the by Uwe Hermann · 17 years ago
  31. 908ff5e This patch masks the function prototypes in stdlib.h from ROMCC, so that by Corey Osgood · 17 years ago
  32. b294582 Add PCI IDs for most Intel southbridges of the 82801 series by Uwe Hermann · 17 years ago
  33. a358892 * Change one PCI vendor ID from Nvidia to SiS by Carl-Daniel Hailfinger · 17 years ago
  34. f7daa0b Various cosmetics, coding style fixes, constifications (trivial). by Uwe Hermann · 17 years ago
  35. a29ec06 Restructure the PCI IDs list for the ICH* chipsets from ICH/ICH0 up to by Uwe Hermann · 17 years ago
  36. 02b2365 This patch is some small changes to the vt8237r to prepare it for by Corey Osgood · 17 years ago
  37. b45bfab remaining part of the patch. by Stefan Reinauer · 17 years ago
  38. aa2a670 Delete a file no longer used by the SiS implementation by Jordan Crouse · 17 years ago
  39. 218c265 1. vgabios removed, will go to extra repository by Morgan Tsai · 17 years ago
  40. 9c84a46 trivial fix for the .data problem by Stefan Reinauer · 17 years ago
  41. 68d8a56 Various fixes and improvements of the 82801xx code. by Joseph Smith · 17 years ago
  42. 418bc91 Add support for the VIA VT8237R southbridge. by Rudolf Marek · 17 years ago
  43. 83b52e7 fix the readwrite/readonly clashes for the pci_driver structs in the sis by Stefan Reinauer · 17 years ago
  44. 1602dd5 Thanks to the great efforts of Morgan Tsai of SiS we support the SiS966 by Morgan Tsai · 17 years ago
  45. a9e5821 smaller changes to silence build warnings. (trivial) by Stefan Reinauer · 17 years ago
  46. f1cf1f7 Ever wondered where those "setting incorrect section attributes for by Stefan Reinauer · 17 years ago
  47. 1d4fc0c This patch adds support for K8T890CE northbridge. by Rudolf Marek · 17 years ago
  48. 37f1669 Fix some issues with spaces in the code and Doxygen style documentation. by Juergen Beisert · 17 years ago
  49. 4ac3217 by Juergen Beisert · 17 years ago
  50. 3617103 Thee lines in i82801xx_pci.c need to be removed. They cause the by Joseph Smith · 17 years ago
  51. f845e02 As per suggestion from Yinghai Lu <yinghailu@gmail.com> this patch by Uwe Hermann · 17 years ago
  52. 3a9740d Fix another, similar typo as in r2800 (trivial). Reported by Robert Millan. by Uwe Hermann · 17 years ago
  53. aa8e9bd Fix typo which causes build error if CK804_USE_NIC is set (trivial). by Uwe Hermann · 17 years ago
  54. 18c70d7 More range for HT_CHAIN_UNITID_BASE and HT_CHAIN_END_UNITID_BASE. by Yinghai Lu · 17 years ago
  55. 3335adb This is a full rewrite of all the CS5530/CS5530A code. The previous code was by Uwe Hermann · 17 years ago
  56. dfb3c13 Various minor cosmetics and coding style fixes (trivial). by Uwe Hermann · 17 years ago
  57. c72ff11 The GPIOs used for UART2 RX and TX were reversed. by Marc Jones · 17 years ago
  58. d9e56e9 Small bugfix in i82801xx_lpc.c. by Corey Osgood · 17 years ago
  59. e99bd10 This patch adds support for the Intel i82810 northbridge and various i82801xx by Corey Osgood · 17 years ago
  60. 56a9125 Intel 82371EB: Some code simplifications (trivial). by Uwe Hermann · 17 years ago
  61. f027280 The UART disable code was causing a hang and was worked around with a by Marc Jones · 17 years ago
  62. 1410c2d Intel 82371EB: Add IDE init support. by Uwe Hermann · 17 years ago
  63. 4cb8553 Init for the Intel 82371EB southbridge: make all ROM/BIOS regions by Uwe Hermann · 17 years ago
  64. 63b087a Drop the src/southbridge/amd/cs5536_lx directory and its contents, as by Uwe Hermann · 17 years ago
  65. 344e457 Add missing license headers, minor cosmetic fixes in existing headers. by Uwe Hermann · 17 years ago
  66. d03b7d4 This fix properly hides the UDC and OTG PCI headers when the cs5536 is by Marc Jones · 17 years ago
  67. ddf845f This patch cleans up and clarifies Geode source code comments. by Marc Jones · 17 years ago
  68. a909ee6 This patch updates the PCI ID of the Geode IDE device to include the revision. by Marc Jones · 17 years ago
  69. 2a133f7 Fix the indent and whitespace to match LinuxBIOS standards by Jordan Crouse · 17 years ago
  70. 4fcb3ba Add missing licenses to several of the files. by Jordan Crouse · 17 years ago
  71. 5ef8b0f by Ronald G. Minnich · 17 years ago
  72. b93f9ca by Ben Hewson · 17 years ago
  73. a67d4fd This patch re-implements support for the CS5536 companion chip for the by Marc Jones · 17 years ago
  74. d436a4b Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB, by Uwe Hermann · 17 years ago
  75. 0888c36 Fix epia-m build after u8/u16/u32 changes in Yh Lu's patch. by Peter Stuge · 17 years ago
  76. 36b601c Add initial pre-RAM serial output support for the VIA VT82C686(A/B) by Corey Osgood · 17 years ago
  77. 8a20213 Fix some CHIP_NAME() entries to use canonical names. by Uwe Hermann · 17 years ago
  78. c5708d1 Nvidia MCP55 uses CMD to send/receive bytes instead of DAT0, by bxshi · 17 years ago
  79. 958a1f3 I have Sun Ultra40 workstation. Southbridge is nVidia CrushK8-04/nforce by Roman Kononov · 17 years ago
  80. c3aaf6a This patch adds the MCP55 PCI IDs (without which the southbridge code by Ed Swierk · 17 years ago
  81. c65bd56 Add support for the NVIDIA MCP55 southbridge. by Yinghai Lu · 17 years ago
  82. 9095e30 A patch to add initial support for the i82801db southbridge based by Jon Dufresne · 17 years ago
  83. 6c3874e ck804 pref mem 4G above support by Yinghai Lu · 17 years ago
  84. 2089487 In the file mainboard/intel/i82801dbm/i82801dbm.c the variable by Jon Dufresne · 17 years ago
  85. f3938bb In src/southbridge/intel/i82801ca, first the smbus registers are mapped at i/o by chn · 17 years ago
  86. a7aa29b Use the canonical name of the vendors/devices and the by Uwe Hermann · 18 years ago
  87. faea4c5 Sorry, this is the last commit I will do this way, but MSI has waited a by bxshi · 18 years ago
  88. a112bb0 s2895 failover build by Yinghai Lu · 18 years ago
  89. 0ab46b9 return missed by Yinghai Lu · 18 years ago
  90. 5f9624d CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support in serengeti_cheeatah by Yinghai Lu · 18 years ago
  91. d4b278c AMD Rev F support by Yinghai Lu · 18 years ago
  92. 2ad85db Lots of lx fixes. CLeanup mainly. THings now build by Ronald G. Minnich · 18 years ago
  93. a341ee2 put this in the right place. by Ronald G. Minnich · 18 years ago
  94. 4d6810c add the _lx flavor of the 5536. This will later be merged into the by Ronald G. Minnich · 18 years ago
  95. b9c100b add file for dcon support by Jordan Crouse · 18 years ago
  96. 66c335b fix cardbus interrups (signed off by Nick Barker) by Stefan Reinauer · 18 years ago
  97. bcd1f23 - Much better USB P4 fix. by Richard Smith · 18 years ago
  98. fa60e7f - USB P4 as host fix by Richard Smith · 18 years ago
  99. 64443b8 - fix a silly pointer dereference thinko in my previous commit by Richard Smith · 18 years ago
  100. 59ba228 - Added suport for enabling USB P4 on the olpc by Richard Smith · 18 years ago