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review.coreboot.org / coreboot / d3f01b21fa7bf9bf115088ddc032aa1cd0000945 / src / southbridge / intel / lynxpoint / pch.c
  1. d3f01b2 sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports by Tristan Corrick · 6 years ago
  2. 1dcd8db src/southbridge: Get rid of device_t by Elyes HAOUAS · 6 years ago
  3. 38f1d13 src/{sb/intel,mb/google/auron}: Don't use device_t by Elyes HAOUAS · 6 years ago
  4. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  5. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  6. c0254e6 lynxpoint: disable pcie devices based on config by Aaron Durbin · 11 years ago
  7. 60f8208 lynxpoint: move all pcie device handling to pcie.c by Aaron Durbin · 11 years ago
  8. 3fcd356 lynxpoint: expose pch_disable_devfn() by Aaron Durbin · 11 years ago
  9. c17aac3 lynxpoint: expose iobp functions by Aaron Durbin · 11 years ago
  10. 98c4062 lynxpoint: Enable SerialIO clock in PCI mode by Duncan Laurie · 11 years ago
  11. 5605f1b Fix compilation of Intel LynxPoint based boards by Stefan Reinauer · 11 years ago
  12. 1ad5564 lynxpoint: Add helper functions for reading PM and GPIO base by Duncan Laurie · 11 years ago
  13. 5cc51c0 lynxpoint: Add function for checking for LP chipset by Duncan Laurie · 11 years ago
  14. 71346c0 lynxpoint: Add support for disabling ULT devices by Duncan Laurie · 12 years ago
  15. 26e7dd7 haswell: more ULT/LP support and minor tweaks by Duncan Laurie · 12 years ago
  16. 7302d1e lynxpoint: Update IOBP programming method by Duncan Laurie · 12 years ago
  17. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago