1. dc93affe by Ward Vandewege · 14 years ago
  2. a2c951e Clean up whitespace and comments style. (trivial) by Marc Jones · 14 years ago
  3. 5f1037c Initial support for the ASI MB-5BLGP (Neoware Eon 4000s). by Uwe Hermann · 14 years ago
  4. 9ecf8fb Remove welcome message from elfboot. None of the other subsystems have their by Stefan Reinauer · 14 years ago
  5. 912857e fix lots of warnings for cache as ram builds (trivial) by Stefan Reinauer · 14 years ago
  6. 87c938f adapt Uncompressing.. patch for AMD code. Also replace "linxbios" by "coreboot" by Stefan Reinauer · 14 years ago
  7. 6852406 Go back to SIPI WAIT state for those CPUS defining the newly introduced by Stefan Reinauer · 14 years ago
  8. a56edac This patch by Stefan Reinauer · 14 years ago
  9. db1b608 oops, forgot these in the cleanup.. (trivial) by Stefan Reinauer · 15 years ago
  10. 11a2014 a heuristics is something different by Stefan Reinauer · 15 years ago
  11. 75f519c Typo, thanks to Idwer for spotting this. (trivial patch) by Stefan Reinauer · 15 years ago
  12. 51754a3 clarify in the printks what function is actually called. This little smart magic by Stefan Reinauer · 15 years ago
  13. 1409136 clean out obsoleted config.lb rules and output, fix indenting (trivial) by Stefan Reinauer · 15 years ago
  14. 48b85fc use printk, when possible. (trivial) by Stefan Reinauer · 15 years ago
  15. 5a522d4 match against all steppings of a CPU model, because these are _model_ drivers. by Stefan Reinauer · 15 years ago
  16. ac555b1 serial.inc is not used anywhere. drop it (trivial) by Stefan Reinauer · 15 years ago
  17. 57d2af8 same spelling in all mtrr output.. (trivial) by Stefan Reinauer · 15 years ago
  18. df6c858 drop unused code (trivial) by Stefan Reinauer · 15 years ago
  19. 96a6036 coding style fixes (trivial) by Stefan Reinauer · 15 years ago
  20. 20ffc03 fix compile warnings of rom_stream.c (trivial) by Stefan Reinauer · 15 years ago
  21. 951c62f add some SPD values from specs. (trivial) by Stefan Reinauer · 15 years ago
  22. a91e0fe function prototypes don't need extern. (trivial) by Stefan Reinauer · 15 years ago
  23. 749c05e fix warning in vga console code (trivial) by Stefan Reinauer · 15 years ago
  24. fec2c4f fix typo in coreboot_ram.ld comment (trivial) by Stefan Reinauer · 15 years ago
  25. bba53ed fix typo in commend of generic_sdram.c (trivial) by Stefan Reinauer · 15 years ago
  26. 3c580b5 clean up comment in onboard.c (trivial) by Stefan Reinauer · 15 years ago
  27. 807dec0 clean up Config.lb in lib/ (trivial) by Stefan Reinauer · 15 years ago
  28. 7a4f688 fix warnings, make mptable struct members explicitly packed, as they're by Stefan Reinauer · 15 years ago
  29. d98cf5b fix typos and warnings in the device tree code (trivial) by Stefan Reinauer · 15 years ago
  30. 96e3022 This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai. by Roman Kononov · 15 years ago
  31. 2aa804f Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how it by Marc Jones · 15 years ago
  32. 35b5361 Add AMD Fam10 B3 default settings to match AMD example code. by Marc Jones · 15 years ago
  33. 51737cf Update to the latest AMD Fam10 microcode patches. by Marc Jones · 15 years ago
  34. c3ec1ac Memory initialization support for AMD Fam10 B3 (B0-B2 already supported). by Marc Jones · 15 years ago
  35. 3a85563 Missed a const in my previous checkin, r3426 (trivial). by Marc Jones · 15 years ago
  36. 3d135e6 Add support for the Winbond W83697HF Super I/O. by Sean Nelson · 15 years ago
  37. eafcedd Add manual HT BUID fixup to detect previously set BUIDs in early init. This fixes the non-coherent(sb) link running at default speed. by Marc Jones · 15 years ago
  38. 212486e Clean up AMD FAM10 HT variable initialization. The structure init is cleaner, avoid compiler warnings, and matches the AMD example code more closely. by Marc Jones · 15 years ago
  39. 2df2915 Add Fam10 Gart table walk enable for MCA reporting to match AMD example code. by Marc Jones · 15 years ago
  40. aee0796 Clean up comments, whitespace, and copyright date in the AMD HT code. by Marc Jones · 15 years ago
  41. 049814c Add missing Intel CPU (trivial). by Uwe Hermann · 15 years ago
  42. 2c39c4c There was a programming error which made most USB port4 setup wrong. This patch uses byte pointer and the MMIO read and write functions. by Marc Jones · 15 years ago
  43. c2e8fd4 Adds a field to the serial port descriptor about the configured line speed. by Patrick Georgi · 15 years ago
  44. 98f32bf Initial support for the A-Trend ATC-6240 board. by Uwe Hermann · 15 years ago
  45. fb73fa1 by Ronald Hoogenboom · 15 years ago
  46. 14669ae This patch allows support for multiple so-dimms, single or double sided. by Joseph Smith · 15 years ago
  47. 4e48408 Extend the VIA vt8237r southbridge decode range for the ROM to 1MB. by Bari Ari · 15 years ago
  48. 4231979 This is a simple patch which allows payloads to be placed in memory in by Myles Watson · 15 years ago
  49. 9d10dc4 Add post-RAM init code for the Fintek F71805F Super I/O. by Corey Osgood · 15 years ago
  50. fcb2a31 Add support for the VIA EPIA-CN baord, which uses C7 + CN700 + VT8237R. by Aaron Lwe · 15 years ago
  51. 85e46e6 Doesn't have to be executable (trivial). by Uwe Hermann · 15 years ago
  52. 2ee5c9e Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all by Marc Jones · 15 years ago
  53. 0fd8ccd New Target and initial support for the Thomson IP1000. by Joseph Smith · 15 years ago
  54. da69582 This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge. by Joseph Smith · 15 years ago
  55. fa36f50 coreboot-v2: Disable second serial port on Norwich by Jordan Crouse · 15 years ago
  56. 83a965d Implement GPIO configuration routines for the Intel 3100 southbridge, by Ed Swierk · 15 years ago
  57. 9d9518f cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a by Marc Jones · 15 years ago
  58. 2342f8b This patch adds pc keyboard init function call for qemu in v2 since some payloads assume by Aaron Lwe · 15 years ago
  59. 4f91417 Fix various issues on MSI MS-7135 board. by Jonathan A. Kollasch · 15 years ago
  60. a9a5f49 By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 by Ed Swierk · 15 years ago
  61. 65e0804 Remove inline from FAM10 CPU initialization functions. by Marc Jones · 15 years ago
  62. 7ca3ec2 Fix so pci device memory allocation does not use memory base address at 0xfec00000, this is reserved for APIC. by Aaron Lwe · 15 years ago
  63. c1cbff2 Add CPUID processor name string support for Fam10 CPUs. by Marc Jones · 15 years ago
  64. 403b89a On APs the ClLinesToNbDis was being left enabled from CAR setup. by Marc Jones · 15 years ago
  65. 202625e This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX) by Nikolay Petukhov · 15 years ago
  66. 3d1d3b2 by Myles Watson · 15 years ago
  67. 0eec1a8 by Myles Watson · 15 years ago
  68. c4a4116 by Ward Vandewege · 15 years ago
  69. a74a8ff Clean up and remove late initialization code that is no longer needed. by Marc Jones · 15 years ago
  70. f0174b5 Find matching settings for each CPUs FID, VID, and P-state registers and initialize them. by Marc Jones · 15 years ago
  71. 8127dc4 Update the FAM10 microcode to current versions. by Marc Jones · 15 years ago
  72. c74e362 Missed this file in the previous check-in, r3248. by Marc Jones · 15 years ago
  73. da4ce6b Add early MSR and PCI register initialization. by Marc Jones · 15 years ago
  74. 7bc63fd This trivial patch adds the SMSC SCH3112 Super I/O chip ID to the by Christopher Kilgour · 15 years ago
  75. e3aeb93 Bring Fam10 memory controller init up to date with the latest AMD BKDG by Marc Jones (marc.jones · 15 years ago
  76. 78f59f8 Re-add files I deleted by mistake in r3219. They are meant for a different by Marc Jones (marc.jones · 15 years ago
  77. df22f78 Don't check exclusive IRQ fieldin the PIR table. by Marc Jones(marc.jones · 15 years ago
  78. 0dc5697 This patch halts the tco timer early in the boot process on all ICH series southbridges. by Joseph Smith · 15 years ago
  79. 4afb7fb Add a workaround for a bug in some binutils version which strictly by Carl-Daniel Hailfinger · 15 years ago
  80. 2b85b63 Setting an integrated southbridge device (like SATA or USB2.0) to by Ed Swierk · 15 years ago
  81. 23cd49a Remove i82801DB files that I meant to delete in r3206. by Joseph Smith · 15 years ago
  82. 06ae639 Tiny style fix for consistency (trivial). by Ed Swierk · 15 years ago
  83. 868de98 Removal of i82801DB (ICH4) by Joseph Smith · 15 years ago
  84. c4e052c The early init code of several Intel southbridge chipsets calls by Ed Swierk · 15 years ago
  85. 71f846c Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots by Ed Swierk · 15 years ago
  86. 1e185e8 Add support for the TeleVideo TC7020. by Kenji Noguchi · 15 years ago
  87. 9c2255c Now coreboot performs IRQ routing for some boards. by Nikolay Petukhov · 15 years ago
  88. da0efc4 Fix for irq routing issues. by Joseph Smith · 15 years ago
  89. 316e07f Following patch adds K8M890 support. It initializes the AGP and graphics UMA. by Rudolf Marek · 15 years ago
  90. c221349 Following patch will setup KT890 HT automatically. It will find the by Rudolf Marek · 15 years ago
  91. cfcc9ca * split model_centaur into model_c3 and model_c7 by Stefan Reinauer · 15 years ago
  92. a2ccf9f Add support for the MSI MS-6119 mainboard. by Uwe Hermann · 15 years ago
  93. fa510c7 Clarify LZMA code license. by Carl-Daniel Hailfinger · 15 years ago
  94. 4f83d7e oops. sorry, wrong checkin. This patch backs out r3155 and instead contains the by Ed Swierk · 15 years ago
  95. 354e2d3 This patch implements support for the Intel 3100 Development Kit by Ed Swierk · 15 years ago
  96. a9faea8 This patch implements support for the Intel 3100 integrated by Ed Swierk · 15 years ago
  97. aaea11b Here is an updated patch addressing most of Uwe's and Peter's by Ed Swierk · 15 years ago
  98. 62eee3f This patch implements support for the Intel 3100 integrated SuperIO and UART. by Ed Swierk · 15 years ago
  99. 791265a This patch updates the PCI IDs for Intel 3100 devices. by Ed Swierk · 15 years ago
  100. 5671787 Following patch extends the ROM decoding to last 1MB, allowing to use larger by Rudolf Marek · 15 years ago