Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
cf32fd172928467ac5bbd4fb372b71230c81cf12
/
src
/
soc
/
intel
/
cannonlake
/
romstage
/
fsp_params.c
cf32fd1
soc/intel/common: Remove common chip config use_fsp_mp_init
by Subrata Banik
· 6 years ago
bfe4a59
soc/intel/cannonlake: Pass coreboot debug interface info to FSP
by Maulik V Vaghela
· 5 years ago
cd49cce
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
by Julius Werner
· 5 years ago
6527b1a
soc/intel/cannonlake: Add Whiskeylake SoC kconfig
by Subrata Banik
· 6 years ago
52b5b58
soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery
by Duncan Laurie
· 6 years ago
0bc3e3d
soc/intel/cannonlake: Enable/Disable IPU based on devicetree switch
by V Sowmya
· 6 years ago
3ef7449
soc/intel/cannonlake: Auto turn on HDA controller
by Lijian Zhao
· 6 years ago
fd02ff0
soc/intel/cannonlake: Enable CPU flexible ratio
by Lijian Zhao
· 6 years ago
25b387a
soc/intel/cannonlake: Remove SmbusEnable
by Duncan Laurie
· 6 years ago
fe701ee
soc/intel/cannonlake: Enable ISH from device
by Lijian Zhao
· 6 years ago
521e48c
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
by praveen hodagatta pranesh
· 6 years ago
e26c4a4
soc/intel/cannonlake: Add new cannon lake PCH-H support
by praveen hodagatta pranesh
· 6 years ago
742c6fe
soc/intel/cannonlake: Move the FSP related callbacks to separate files
by Rizwan Qureshi
· 6 years ago