1. 716738a x86: add cache-as-ram migration option by Aaron Durbin · 10 years ago
  2. 38c326d x86: add thread support by Aaron Durbin · 10 years ago
  3. 703aa97 x86: harden tsc udelay() function by Aaron Durbin · 10 years ago
  4. 8e73b5d x86: add TSC_CONSTANT_RATE option by Aaron Durbin · 10 years ago
  5. e850164 tsc: provide monotonic timer by Aaron Durbin · 10 years ago
  6. fd8291c lapic: monotonic time implementation by Aaron Durbin · 10 years ago
  7. bebf669 x86: use boot state callbacks to disable rom cache by Aaron Durbin · 10 years ago
  8. 190011e AMD: Drop six copies of wrmsr_amd and rdmsr_amd by Kyösti Mälkki · 10 years ago
  9. ebf142a boot: add disable_cache_rom() function by Aaron Durbin · 10 years ago
  10. 5392424 x86: mtrr: optimize hole carving above 4GiB by Aaron Durbin · 10 years ago
  11. e383442 x86: mtrr: add hole punching support by Aaron Durbin · 10 years ago
  12. bc07f5d x86: add rom cache variable MTRR index to tables by Aaron Durbin · 10 years ago
  13. 77a5b40 x86: mtrr: add CONFIG_CACHE_ROM support by Aaron Durbin · 10 years ago
  14. 9b027fe mtrr: honor IORESOURCE_WRCOMB by Aaron Durbin · 10 years ago
  15. bb4e79a x86: add new mtrr implementation by Aaron Durbin · 10 years ago
  16. 57686f8 x86: unify amd and non-amd MTRR routines by Aaron Durbin · 10 years ago
  17. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 10 years ago
  18. a146d58 ramstage: prepare for relocation by Aaron Durbin · 10 years ago
  19. c2fe1e0 SMM: link against libgcc by Stefan Reinauer · 10 years ago
  20. 8e345d4 haswell: lapic timer support by Aaron Durbin · 10 years ago
  21. 29ffa54 haswell: Use SMM Modules by Aaron Durbin · 10 years ago
  22. 69efaa0 Google Link: Add remaining code to support native graphics by Ronald G. Minnich · 10 years ago
  23. 50a3464 x86: SMM Module Support by Aaron Durbin · 10 years ago
  24. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 10 years ago
  25. ae0e8d3 Eliminate do_div(). by David Hendricks · 10 years ago
  26. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 10 years ago
  27. 62f100b smm: Update rev 0x30101 SMM revision save state by Aaron Durbin · 10 years ago
  28. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 10 years ago
  29. 399486e Unify assembler function handling by Stefan Reinauer · 10 years ago
  30. e135ac5 Remove AMD special case for LAPIC based udelay() by Patrick Georgi · 10 years ago
  31. e72a8a3 intel/i82801ix: new southbridge, ICH9 by Patrick Georgi · 10 years ago
  32. 82ecf4c secondary.S: Fix dropping ramstage.a by Stefan Reinauer · 10 years ago
  33. 40f36e0 Make sure only one udelay function is available by Stefan Reinauer · 10 years ago
  34. 75dbc38 Clean up stack checking code by Stefan Reinauer · 10 years ago
  35. 1bfbbc0 clean up lapic_cpu_init.c by Stefan Reinauer · 11 years ago
  36. 8b93059 Pass the CPU index as a parameter to startup. by Ronald G. Minnich · 11 years ago
  37. 000bf83 Support better tracking of AP stack usage. by Ronald G. Minnich · 11 years ago
  38. a571c70 Fix gcc-4.7 building problem. by Han Shen · 10 years ago
  39. 0db6820 Synchronize rdtsc instructions by Stefan Reinauer · 11 years ago
  40. 7bdf85b Move cpus_ready_for_init() to AMD K8 by Kyösti Mälkki · 11 years ago
  41. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 11 years ago
  42. 51676b1 Revert "Use broadcast SIPI to startup siblings" by Sven Schnelle · 11 years ago
  43. a2701c6 Revert "remove CONFIG_SERIAL_CPU_INIT" by Sven Schnelle · 11 years ago
  44. 82704c6 USBDEBUG: buffer up to 8 bytes by Sven Schnelle · 11 years ago
  45. 62f1ad9 SMM: Fix state table for Intel Core2 CPUs by Stefan Reinauer · 11 years ago
  46. 8d32b89 Fix LAPIC timer on Ivy Bridge systems by Stefan Reinauer · 11 years ago
  47. 51cb26d SMM: Fix state save map for sandybridge and TSEG by Duncan Laurie · 11 years ago
  48. d2e00b9 SMM: Add heap region and move C handler higher in region by Duncan Laurie · 11 years ago
  49. b91a0f2 Rename cache_lbmem() to cache_ramstage() by Stefan Reinauer · 11 years ago
  50. 0067188 MTRR: drop repetetive debug message by Stefan Reinauer · 11 years ago
  51. ac2ec34 Re-initialize Local APIC timer on APs by Stefan Reinauer · 11 years ago
  52. 2d42b34 Check for IORESOURCE_UMA_FB in MTRR setup by Kyösti Mälkki · 11 years ago
  53. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 11 years ago
  54. ffc1fb3 Drop Kconfig VAR_MTRR_HOLE option by Kyösti Mälkki · 11 years ago
  55. 6f73a5b Fix stack assignment during CPU initialization by Sven Schnelle · 11 years ago
  56. 63539bb Only copy real-mode section of SIPI vector by Kyösti Mälkki · 11 years ago
  57. 9a663f3 Fix the CPU index parameter passed to secondary_cpu_init(). by Kyösti Mälkki · 11 years ago
  58. 78efc4c remove CONFIG_SERIAL_CPU_INIT by Sven Schnelle · 11 years ago
  59. 042c146 Use broadcast SIPI to startup siblings by Sven Schnelle · 11 years ago
  60. 0860e72 udelay: add missing bus frequency by Sven Schnelle · 11 years ago
  61. 7c2d058 Fix the location of "Setting variable MTRR" printk. by Denis 'GNUtoo' Carikli · 11 years ago
  62. f8f0062 Some more #if cleanup by Patrick Georgi · 11 years ago
  63. e166782 Clean up #ifs by Patrick Georgi · 11 years ago
  64. d6e4d51 Revert wbind added to the reset_vector by Marc Jones · 11 years ago
  65. 05758bd Remove obsolete empy macro definition by Ron Minnich · 11 years ago
  66. 2bdfb48 Fixes and Sandybridge support for lapic cpu init by Stefan Reinauer · 11 years ago
  67. 334532e Add Sandybridge/Cougar Point support to SMM relocation handler by Stefan Reinauer · 11 years ago
  68. c00dfbc Cache 8MB flash instead of 4MB by Stefan Reinauer · 11 years ago
  69. 5b6404e Fix timer frequency detection on Sandybridge by Stefan Reinauer · 11 years ago
  70. deda997 Invalidate cache before first jump by Stefan Reinauer · 11 years ago
  71. 8c5b58e Update documentation in smmrelocate.S to mention TSEG by Stefan Reinauer · 11 years ago
  72. 3aa067f Add support to run SMM handler in TSEG instead of ASEG by Stefan Reinauer · 11 years ago
  73. 7b67892 Make MTRR min hole alignment 64MB by Duncan Laurie · 11 years ago
  74. 527fc74 Fix MB calculation in the reporting of the MTRR hole by Duncan Laurie · 11 years ago
  75. 7389fa9 MTRR: add alternate allocation method for odd memory maps by Duncan Laurie · 11 years ago
  76. 8bb7723 Add Kconfig options to enable TSEG and set a size by Duncan Laurie · 11 years ago
  77. 67aa3d6 drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed by Stefan Reinauer · 11 years ago
  78. 00093a8 Add an option to keep the ROM cached after romstage by Stefan Reinauer · 11 years ago
  79. a01ae62 Fix possible deadlock on SMP stop_this_cpu by Kyösti Mälkki · 11 years ago
  80. 1c93d90 ROMCC boards have no XIP limit by Patrick Georgi · 11 years ago
  81. 7863015 Fix address of IDT in real-mode entry by Kyösti Mälkki · 11 years ago
  82. 8907e81 move console includes to central console/console.h by Stefan Reinauer · 12 years ago
  83. c5fc7db Move C labels to start-of-line by Patrick Georgi · 11 years ago
  84. 472efa6 Remove whitespace. by Patrick Georgi · 11 years ago
  85. 0713ca3 post code: Replaced hard-coded post code with macro by Vikram Narayanan · 11 years ago
  86. 15370ca trivial: spelling fixes in comments by Vikram Narayanan · 11 years ago
  87. c6daaa7 Leave SSE and MMX instructions enabled in coreboot by Stefan Reinauer · 11 years ago
  88. adfbcb79 MTRR: get physical address size from CPUID by Sven Schnelle · 11 years ago
  89. eafb18b Bootblock does not need a unique boot_cpu() by Kyösti Mälkki · 11 years ago
  90. 0dbfb54 Remove unused code files and cosmetic changes by Kyösti Mälkki · 11 years ago
  91. 2a40ebc Fix post_code in 16bit entry by Kyösti Mälkki · 11 years ago
  92. 5ff7c13 remove trailing whitespace by Stefan Reinauer · 11 years ago
  93. 784544b Remove XIP_ROM_BASE by Patrick Georgi · 11 years ago
  94. 1da1046 Get rid of AUTO_XIP_ROM_BASE by Patrick Georgi · 11 years ago
  95. 3128685 SMM: Move wbinvd after pmode jump by Stefan Reinauer · 11 years ago
  96. 71496be Load an IDT with NULL limit by Stefan Reinauer · 12 years ago
  97. 78834b7 Miscellaneous AMD F14 warning fixes by efdesign98 · 12 years ago
  98. 3cab93c Add SSE3 dependent code by efdesign98 · 12 years ago
  99. 7f76290 Small SMM fixups by Rudolf Marek · 12 years ago
  100. 47b3fb4 SMM: flush caches after disabling caching by Sven Schnelle · 12 years ago