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review.coreboot.org / coreboot / cb141bce35d6b0ee08a14c1097fa19bc10e4d9e7 / src / include / device / pci_def.h
  1. cb141bc usbdebug: Split PCI EHCI part by Kyösti Mälkki · 11 years ago
  2. c73acdb Add test to match struct device with pci_devfn_t by Kyösti Mälkki · 11 years ago
  3. 0cb07e3 include: Fix spelling by Martin Roth · 11 years ago
  4. 90dcdd4 Add support for enabling PCIe Common Clock and ASPM by Duncan Laurie · 13 years ago
  5. 14e2277 Since some people disapprove of white space cleanups mixed in regular commits by Stefan Reinauer · 14 years ago
  6. 4855f56 add define for Role-Based Error Reporting to PCIe defines (trivial) by Stefan Reinauer · 15 years ago
  7. d4b278c AMD Rev F support by Yinghai Lu · 18 years ago
  8. 13f1c2a eric patch by Yinghai Lu · 19 years ago
  9. 992cd00 - Update the device header files by Eric Biederman · 20 years ago
  10. 5cd8173 - Moved hlt() to it's own header. by Eric Biederman · 20 years ago
  11. 860ad37 - First pass at code for generic link width and size determination by Eric Biederman · 21 years ago
  12. a05b6dd - Add pci_def.h so romcc compiled files can also get at the pci definitions by Eric Biederman · 21 years ago