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coreboot
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c9bf446ee93fb2334117b97e8ed94b8f78e6856d
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src
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soc
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intel
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baytrail
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xhci.c
c9bf446
baytrail: Change USB3 PLL VCO and iCLK PLL current on BYT-M/D CPU
by Kein Yuan
· 10 years ago
9e94dbf
ACPI: Get S3 resume state from romstage_handoff
by Kyösti Mälkki
· 10 years ago
51d787a
rambi/baytrail: ACPI, GPIO, audio, misc updates
by Shawn Nematbakhsh
· 11 years ago
616f394
baytrail: utilize reg_script_run_on_dev()
by Aaron Durbin
· 11 years ago
a90a59f5
baytrail: Fix XHCI problems and re-enable
by Duncan Laurie
· 11 years ago
f81a91a
baytrail: Add XHCI initialization
by Duncan Laurie
· 11 years ago