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coreboot
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c6f27226a84434182771dbbcd593d223072801f7
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src
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northbridge
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intel
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sandybridge
/
northbridge.c
c6f2722
sandybridge: enable ROM caching
by Aaron Durbin
· 11 years ago
c965076
resources: introduce reserved_ram_resource()
by Aaron Durbin
· 11 years ago
a46a712
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
by Paul Menzel
· 11 years ago
fd611f9
Drop CONFIG_WRITE_HIGH_TABLES
by Stefan Reinauer
· 11 years ago
0aa37c4
sconfig: rename lapic_cluster -> cpu_cluster
by Stefan Reinauer
· 12 years ago
4aff445
sconfig: rename pci_domain -> domain
by Stefan Reinauer
· 12 years ago
5079a0d
Remove assembly coded log2 function
by Ronald G. Minnich
· 12 years ago
cf8e466
Cleanup coreboot memory table includes
by Kyösti Mälkki
· 12 years ago
9ca1c0a
Sandy/Ivy Bridge and Cougar/Panther Point: Fix names
by Stefan Reinauer
· 12 years ago
5e29f00
Intel and GFXUMA: drop redundant use of lb_add_memory_range()
by Kyösti Mälkki
· 12 years ago
7f189cc
Intel Sandybridge and UMA: use mmio_resource()
by Kyösti Mälkki
· 12 years ago
1ec5e74
Intel Sandybridge: add reserved memory as resources
by Kyösti Mälkki
· 12 years ago
fe7b5d2
Ivybridge: fix workaround and enable PAIR
by Duncan Laurie
· 12 years ago
77dbbac
CPU: Add basic support for Nominal Configurable TDP
by Duncan Laurie
· 12 years ago
496f4a0
SandyBridge: Add another PCI device ID for northbridge
by Walter Murphy
· 12 years ago
cc55b9b
Define global uma_memory variables
by Kyösti Mälkki
· 12 years ago
bb11e60
Hook up MRC cache update
by Stefan Reinauer
· 12 years ago
1244f4b
Rework Sandybridge MRC cache handling
by Stefan Reinauer
· 12 years ago
e166782
Clean up #ifs
by Patrick Georgi
· 12 years ago
0ff99b7
Modify DMI init for IvyBridge
by Vincent Palatin
· 12 years ago
00636b0
Add support for Intel Sandybridge CPU (northbridge part)
by Stefan Reinauer
· 12 years ago