Gitiles
Code Review Sign In
review.coreboot.org / coreboot / c6f27226a84434182771dbbcd593d223072801f7 / src / northbridge / intel / sandybridge / northbridge.c
  1. c6f2722 sandybridge: enable ROM caching by Aaron Durbin · 11 years ago
  2. c965076 resources: introduce reserved_ram_resource() by Aaron Durbin · 11 years ago
  3. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  4. fd611f9 Drop CONFIG_WRITE_HIGH_TABLES by Stefan Reinauer · 11 years ago
  5. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  6. 4aff445 sconfig: rename pci_domain -> domain by Stefan Reinauer · 12 years ago
  7. 5079a0d Remove assembly coded log2 function by Ronald G. Minnich · 12 years ago
  8. cf8e466 Cleanup coreboot memory table includes by Kyösti Mälkki · 12 years ago
  9. 9ca1c0a Sandy/Ivy Bridge and Cougar/Panther Point: Fix names by Stefan Reinauer · 12 years ago
  10. 5e29f00 Intel and GFXUMA: drop redundant use of lb_add_memory_range() by Kyösti Mälkki · 12 years ago
  11. 7f189cc Intel Sandybridge and UMA: use mmio_resource() by Kyösti Mälkki · 12 years ago
  12. 1ec5e74 Intel Sandybridge: add reserved memory as resources by Kyösti Mälkki · 12 years ago
  13. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  14. 77dbbac CPU: Add basic support for Nominal Configurable TDP by Duncan Laurie · 12 years ago
  15. 496f4a0 SandyBridge: Add another PCI device ID for northbridge by Walter Murphy · 12 years ago
  16. cc55b9b Define global uma_memory variables by Kyösti Mälkki · 12 years ago
  17. bb11e60 Hook up MRC cache update by Stefan Reinauer · 12 years ago
  18. 1244f4b Rework Sandybridge MRC cache handling by Stefan Reinauer · 12 years ago
  19. e166782 Clean up #ifs by Patrick Georgi · 12 years ago
  20. 0ff99b7 Modify DMI init for IvyBridge by Vincent Palatin · 12 years ago
  21. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago