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review.coreboot.org / coreboot / c49d7a3e6385a3eb2fae3b6eca36e8ca998f79ad / src / mainboard / pcengines / apu2 / variants / apu3 / devicetree.cb
  1. c49d7a3 src/: Replace GPL boilerplate with SPDX headers by Patrick Georgi · 4 years, 3 months ago
  2. 65f0550 superio/nuvoton/nct5104d: add chip config option to reset GPIOs by Michał Żygowski · 4 years, 6 months ago
  3. 4d177e4 mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe by Michał Żygowski · 4 years, 6 months ago
  4. 078bc41 mainboard/[g-p]*: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  5. 302951d mb/pcengines/*: enable simple IO-based GPIO control by Piotr Kleinschmidt · 4 years, 7 months ago
  6. 941c9ac mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft reset by Piotr Kleinschmidt · 4 years, 7 months ago
  7. 4dba497 binaryPI: Drop nested northbridge in devicetree by Kyösti Mälkki · 6 years ago
  8. 694d18a pcengines/apu2: enable IOMMU for all apu2 variants by Piotr Król · 6 years ago
  9. 36a208d pcengines/apu2: remove TPM from devicetree for apu3 by Piotr Król · 7 years ago
  10. 70b9245 mainboard/pcengines/apu2: add apu3 and apu5 variants by Kamil Wcislo · 7 years ago