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review.coreboot.org / coreboot / c3d03b3197dd5c582c18bcf7b9ececde130d07b3 / src / soc / sifive
  1. d19f4e5 riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV by Ronald G. Minnich · 6 years ago
  2. 0535804 riscv: create Kconfig architecture features for new parts by Ronald G. Minnich · 6 years ago
  3. 1d748c5 console: Change BOOTBLOCK_CONSOLE default to `y` by Nico Huber · 6 years ago
  4. 968a23d riscv: fix non-SMP support by Philipp Hug · 6 years ago
  5. 97ca02c soc/sifive/fu540: Add helper function to get tlclk frequency by Jonathan Neuschäfer · 6 years ago
  6. a09c2e1 soc/sifive/fu540: Load PLL settings from a struct by Jonathan Neuschäfer · 6 years ago
  7. 90fd072 soc/sifive/fu540: Simplify UART refclk calculation by Jonathan Neuschäfer · 6 years ago
  8. 7c9540e riscv: add support smp_pause / smp_resume by Xiang Wang · 6 years ago
  9. bb7f41d sifive/fu540: correct cbmem support by Philipp Hug · 6 years ago
  10. 8ac6a19 soc/sifive/fu540: Document #if ENV_ROMSTAGE line by Jonathan Neuschäfer · 6 years ago
  11. 0fb58f3 soc/sifive/fu540: Remove PLL parameters from sdram.c by Jonathan Neuschäfer · 6 years ago
  12. 4e7a473 sifive/hifive-unleashed: enable CBMEM support by Philipp Hug · 6 years ago
  13. 7c5acd4 soc/sifive: move ram_resource to mainboard by Philipp Hug · 6 years ago
  14. df5e6f6 soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculation by Philipp Hug · 6 years ago
  15. 9159572 soc/sifive/fu540: Initialize SDRAM by Philipp Hug · 6 years ago
  16. 374d992 soc/sifive/fu540: Switch clock to 1GHz in romstage by Philipp Hug · 6 years ago
  17. c014ef5 soc/sifive/fu540: create ram_resource with actual memory size by Philipp Hug · 6 years ago
  18. 199b75f arch/riscv: provide a monotonic timer by Philipp Hug · 6 years ago
  19. 31dbfbc soc/sifive/fu540: add SiFive supplied header files for SDRAM initialization by Philipp Hug · 6 years ago
  20. bdd866e soc/sifive/fu540: Get SDRAM controller out of reset by Philipp Hug · 6 years ago
  21. 18764a3 soc/sifive/fu540: Update clock settings according SiFive bootloader by Philipp Hug · 6 years ago
  22. 7524400 uart/sifive: make divisor configurable by Philipp Hug · 6 years ago
  23. 3d398ad soc/sifive/fu540: Initialize PLL and clock by Philipp Hug · 6 years ago
  24. e056859 soc/sifive: fix compiler warning by Philipp Hug · 6 years ago
  25. 2cf9990 soc/sifive/fu540: Makefile: include mtime_init in ramstage by Philipp Hug · 6 years ago
  26. ea81928 soc/sifive/fu540: Add driver for OTP memory by Philipp Hug · 6 years ago
  27. aa5f821 soc/sifive/fu540: add CLINT support by Xiang Wang · 6 years ago
  28. 2e38dbe riscv: update mtime initialization by Xiang Wang · 6 years ago
  29. a5b265b riscv: separately define stack locations at different stages by Xiang Wang · 6 years ago
  30. 52a022f sifive/fu540: add empty sdram init and size functions by Philipp Hug · 6 years ago
  31. 5fed693 riscv: add support for modifying compiler options by Xiang Wang · 6 years ago
  32. 55b4645 src/sifive: Add the SiFive Freedom Unleashed 540 SoC by Jonathan Neuschäfer · 6 years ago