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review.coreboot.org / coreboot / bfb11bec3b3fec638adf864a9b9b2cff6671fed8 / src / soc / qualcomm / qcs405 / memlayout.ld
  1. 42f1505 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere by Patrick Georgi · 11 months ago
  2. 82d16b1 memlayout: Store region sizes as separate symbols by Julius Werner · 3 years, 8 months ago
  3. baf27db cbfs: Enable CBFS mcache on most chipsets by Julius Werner · 4 years, 11 months ago
  4. 46514c2 treewide: Add Kconfig variable MEMLAYOUT_LD_FILE by Furquan Shaikh · 4 years, 2 months ago[Renamed from src/soc/qualcomm/qcs405/include/soc/memlayout.ld]
  5. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  6. ac95903 treewide: replace GPLv2 long form headers with SPDX header by Patrick Georgi · 4 years, 3 months ago
  7. 02363b5 treewide: Move "is part of the coreboot project" line in its own comment by Patrick Georgi · 4 years, 3 months ago
  8. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  9. cefe89e lib/fmap: Add optional pre-RAM cache by Julius Werner · 4 years, 10 months ago
  10. 0097f55 vboot: standardize on working data size by Joel Kitching · 5 years ago
  11. 717050d qcs405: Add DRAM resources by Nitheesh Sekar · 6 years ago
  12. 20e7587 soc/qualcomm/qcs405: Support for new SoC by Nitheesh Sekar · 6 years ago