Gitiles
Code Review Sign In
review.coreboot.org / coreboot / b8dc63bdfe04fc15553f1ea6e42583cbdaad38ac / src / soc / intel / cannonlake / Kconfig
  1. b8dc63b ic2/designware: Move Intel i2c logic to shared driver by Chris Ching · 7 years ago
  2. 2b96f42 soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region() by Aaron Durbin · 7 years ago
  3. 75c6f4a soc/intel/cannonlake: Make use of Intel common Graphics block by Subrata Banik · 7 years ago
  4. f388561 soc/intel/cannonlake: Define default LPSS clock by Lijian Zhao · 7 years ago
  5. 5a283ef soc/intel/cannonlake: Make use of Intel SPI common block by Subrata Banik · 7 years ago
  6. 7b2d1ae soc/intel/cannonlake: Add DSP support by Lijian Zhao · 7 years ago
  7. 9bb684a soc/intel/cannonlake: Install common i2c by Lijian Zhao · 7 years ago
  8. d2c6365 soc/intel/cannonlake: Use SCS common code by Bora Guvendik · 7 years ago
  9. 899f5ff soc/intel/cannonlake: Use common p2sb driver by Lijian Zhao · 7 years ago
  10. 9b6384c soc/intel/cannonlake: Increase stack size from 4KiB to 8KiB by John Zhao · 7 years ago
  11. c85890d soc/intel/cannonlake: Change max root port to 16 by Lijian Zhao · 7 years ago
  12. b0c4cbb soc/intel/cannonlake: Add IGD Support and pre-OS display code by Abhay Kumar · 7 years ago
  13. 47569cf soc/intel/cannonlake: Use EBDA area to store cbmem_top address by Subrata Banik · 7 years ago
  14. 0c8237a soc/intel/cannonlake: Change default UART number to 2 by Lijian Zhao · 7 years ago
  15. a06f55b soc/intel/cannonlake: Enable MRC cache by Lijian Zhao · 7 years ago
  16. 4a8f45f soc/intel/cannonlake: reduce bootblock size by Aaron Durbin · 7 years ago
  17. f0eb999 soc/intel/cannonlake: Fill the SMI usage by Lijian Zhao · 7 years ago
  18. a515849 soc/intel/cannonlake: Add lpc pci driver by Lijian Zhao · 7 years ago
  19. fcf8820 soc/intel/cannonlake: Add FSP GOP support by Abhay kumar · 7 years ago
  20. 2b074d9 soc/intel/cannonlake: Add common ACPI support for CNL by Lijian Zhao · 7 years ago
  21. 6d7063c soc/intel/cannonlake: Add Vboot/ChromeOS support by Lijian Zhao · 7 years ago
  22. c8c741d soc/intel/cannonlake: Define Max PCIE Root Ports by Pratik Prajapati · 7 years ago
  23. 69b5cdb soc/intel/cannonlake: add gpio files to make by Nick Vaccaro · 7 years ago
  24. d37ebdd soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode by Lijian Zhao · 7 years ago
  25. b045d4c soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLE by Subrata Banik · 7 years ago
  26. 9027e1b soc/intel/cannonlake: Init UPD params based on config by Pratik Prajapati · 7 years ago
  27. 01eda28 soc/intel/cannonlake: Add cpu.c and MP init support by Pratik Prajapati · 7 years ago
  28. b3dfcb8 soc/intel/cannonlake: Enable common PMC code for CNL by Lijian Zhao · 7 years ago
  29. ce4c9ec soc/intel/cannonlake: Add Kconfig option to select UART index by Subrata Banik · 7 years ago
  30. 3211117 soc/intel/cannonlake: Add SPI flash controller driver by Lijian Zhao · 7 years ago
  31. 8465a81 soc/intel/cannonlake: Add postcar stage support by Lijian Zhao · 7 years ago
  32. ae15486 soc/cannonlake: Enable SMM code for Cannon Lake by Brandon Breitenstein · 7 years ago
  33. dcf99b0 soc/intel/cannonlake: Sort Kconfig for Cannonlake by Lijian Zhao · 7 years ago
  34. 80358a1 Revert "soc/intel/cannonlake: Add postcar stage support" by Martin Roth · 7 years ago
  35. 399c022 soc/intel/cannonlake: Add postcar stage support by Lijian Zhao · 7 years ago
  36. a77c68a soc/intel/cannonlake: Make ramstage relocatable by Lijian Zhao · 7 years ago
  37. acfc149 soc/intel/cannonlake: Add microcode support by Lijian Zhao · 7 years ago
  38. c854b49 soc/intel/cannonlake: Use common GPIO driver by Andrey Petrov · 7 years ago
  39. 3e2e050 soc/intel/cannonlake: Add early CPU initialization by Andrey Petrov · 7 years ago
  40. 8109604 soc/intel/cannonlake: Add initial dummy directory by Lijian Zhao · 7 years ago