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review.coreboot.org / coreboot / b890a1228d22b2d48792575986d4750e88751c8b / src / northbridge / intel / sandybridge / early_init.c
  1. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  2. bde6d30 x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer by Kevin Paul Herbert · 10 years ago
  3. a10bde9 intel/sandybridge: Add VGA pci device ID 0x0162 by Damien Zammit · 10 years ago
  4. c845b43 sandybridge: Move common northbridge finalize to northbridge code. by Vladimir Serbinenko · 10 years ago
  5. 5fc04d1 sandy/ivybridge: Make UMA size configurable. by Vladimir Serbinenko · 10 years ago
  6. 54d6abd Drop some duplicates of PCI-e config functions by Kyösti Mälkki · 11 years ago
  7. fbdb085 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT by Kyösti Mälkki · 11 years ago
  8. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  9. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  10. 816e9d1 Support for Celeron 1007U by Stefan Reinauer · 12 years ago
  11. f4d3623 ELOG: Add support for a monotonic boot counter in CMOS by Duncan Laurie · 12 years ago
  12. 9c4c6ab ELOG: Fix boot count increment for non-wake case by Duncan Laurie · 12 years ago
  13. fe7b5d2 Ivybridge: fix workaround and enable PAIR by Duncan Laurie · 12 years ago
  14. afcaac2 Drop (empty) sandybridge_late_initialization() by Stefan Reinauer · 12 years ago
  15. 00636b0 Add support for Intel Sandybridge CPU (northbridge part) by Stefan Reinauer · 12 years ago