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review.coreboot.org / coreboot / b3a8cc54dbaf833c590a56f912209a5632b71f49 / src / soc / intel / cannonlake / fsp_params.c
  1. 8aadab7 soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN# by Rizwan Qureshi · 6 years ago
  2. 4185de5 soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree by Jeremy Soller · 5 years ago
  3. d01a995 src/soc/intel/cannonlake: Add PsysPmax setting by Gaggery Tsai · 6 years ago
  4. 3bb8c24 soc/intel/cannonlake: Configure serial debug uart by Ronak Kanabar · 6 years ago
  5. 3126964 soc/intel/cannonlake: Provide interface to update TCC offset by John Su · 6 years ago
  6. 55012d1 soc/intel/cannonlake: Add FSP UPD for minimum assertion width by Duncan Laurie · 6 years ago
  7. 09f7382 soc/intel/cannonlake: Enable CNVi based on devicetree by Maulik V Vaghela · 6 years ago
  8. 9bf1d8f soc/intel/cannonlake: SATA and DMI power optimize by Lijian Zhao · 6 years ago
  9. ae75400 soc/intel/cannonlake: Add Acoustic features by Lijian Zhao · 6 years ago
  10. 79152f3 soc/intel/cannonlake: Add options for pcie ltr by Lijian Zhao · 6 years ago
  11. ae4eee1 soc/intel/cannonlake: Remove depreciated UPD selection by Lijian Zhao · 6 years ago
  12. 7cf9862 soc/intel/cannonlake: Disable Legacy PME for Root ports by Subrata Banik · 6 years ago
  13. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  14. 742c6fe soc/intel/cannonlake: Move the FSP related callbacks to separate files by Rizwan Qureshi · 6 years ago