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b3a8cc54dbaf833c590a56f912209a5632b71f49
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src
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soc
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intel
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cannonlake
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acpi
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southbridge.asl
088d2a3
soc/intel/cnl/acpi: add ish ACPI device
by Jett Rink
· 5 years ago
75bdd43
soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices
by Subrata Banik
· 6 years ago
69b18f0
mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT generation
by Subrata Banik
· 6 years ago
521e48c
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
by praveen hodagatta pranesh
· 6 years ago
c8a842b
soc/intel/cannonlake: Add PCIE ASL entry
by Subrata Banik
· 6 years ago
a072989
soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
by Subrata Banik
· 6 years ago
1d90093
soc/intel/cannonlake: Add ACPI entry for LAN
by Lijian Zhao
· 6 years ago
d145c95
soc/intel/cannonlake: Fix comment errors for SMBUS
by Lijian Zhao
· 6 years ago
51605e2
soc/intel/cannonlake: Clear EMMC timeout register
by Lijian Zhao
· 6 years ago
20123a8
soc/intel/cannonlake: Use common PCR ASL
by Lijian Zhao
· 7 years ago
1b75994b
src/soc/intel/cannonlake: Add _PRW for CNVi
by Bora Guvendik
· 7 years ago
ae56546
soc/intel/cannonlake: Add all the SOC level DSDT tables
by Lijian Zhao
· 7 years ago
5d11cc9
soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by Bora Guvendik
· 7 years ago
67fb347
soc/intel/cannonlake: Add PCIE IRQs
by Bora Guvendik
· 7 years ago