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review.coreboot.org / coreboot / b15946d72cbf98157ecf5062f5d610f821c0284e / src / soc / intel / cannonlake / romstage / romstage.c
  1. b15946d soc/intel: Add max memory speed into dimm info by Eric Lai · 1 year, 2 months ago
  2. 6be82a4 soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fill by David Milosevic · 1 year, 10 months ago
  3. 0b92aa6 soc/intel: Rename heci_init to cse_init by Subrata Banik · 2 years, 3 months ago
  4. 7c2f57a soc/intel/cnl: Enable CSE FW sync for CSE LITE SKU by Matt DeVillier · 2 years, 6 months ago
  5. 53496e6 soc/intel: Drop `romstage_pch_init()` function by Angel Pons · 3 years, 6 months ago
  6. 53b99a8 soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num() by Nick Vaccaro · 3 years, 11 months ago
  7. 0ed02d0 mb, soc: change mainboard_get_dram_part_num() prototype by Nick Vaccaro · 3 years, 11 months ago
  8. 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
  9. f5627e8 soc/intel/cannonlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 4 months ago
  10. 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
  11. 33ff4cc soc/intel/cannonlake: Refactor pch_early_init() code by Usha P · 4 years, 9 months ago
  12. 32d47eb soc/intel: Rename <intelblocks/chip.h> by Kyösti Mälkki · 5 years ago
  13. 81100bf soc/intel: Move fill_postcar_frame to memmap.c by Kyösti Mälkki · 5 years ago
  14. a7d2f29 intel/car: Use common TS_START_ROMSTAGE by Kyösti Mälkki · 5 years ago
  15. cd7a70f soc/intel: Use common romstage code by Kyösti Mälkki · 5 years ago
  16. a963acd arch/x86: Add <arch/romstage.h> by Kyösti Mälkki · 5 years ago
  17. 6e2d0c1 arch/x86: Adjust size of postcar stack by Kyösti Mälkki · 5 years ago
  18. 1a86cda soc/intel: Provide SPD manufacturer ID and module type to SMBIOS by Duncan Laurie · 5 years ago
  19. f972322 src/soc/intel/common/smbios: Add addtional infos to dimm_info by Christian Walter · 5 years ago
  20. 46340d0 soc/intel: Fill DIMM serial number from SPD by Duncan Laurie · 5 years ago
  21. c338507 soc/{amd,intel}/chip: Use local include for chip.h by Elyes HAOUAS · 5 years ago
  22. cd4fe0f src: include <assert.h> when appropriate by Elyes HAOUAS · 5 years ago
  23. 5c19009 soc/intel/cannonlake: Allow mainboard to override DRAM part number by Furquan Shaikh · 5 years ago
  24. 065857e arch/io.h: Drop unnecessary include by Kyösti Mälkki · 5 years ago
  25. 993f68a soc/intel: Add mem_rank info in SMBIOS by Francois Toguo · 6 years ago
  26. 7e8bad4 soc/intel/cannonlake: Don't use CAR_GLOBAL by Arthur Heymans · 6 years ago
  27. 3da1b0d soc/intel/cannonlake: Fix chipset_power_state structure by Duncan Laurie · 6 years ago
  28. d44221f Move compiler.h to commonlib by Nico Huber · 6 years ago
  29. 742c6fe soc/intel/cannonlake: Move the FSP related callbacks to separate files by Rizwan Qureshi · 6 years ago
  30. a57447d soc/intel/cannonlake: Move SkipMpInit config to FSPM by Lijian Zhao · 6 years ago
  31. 6ea6775 soc/{amd,intel}: Use postcar_frame_add_romcache() by Nico Huber · 6 years ago
  32. 9593e97 soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE) by Nico Huber · 6 years ago
  33. 6403167 compiler.h: add __weak macro by Aaron Durbin · 6 years ago
  34. 26be35a soc/intel/cannonlake: Set DISB after Dram init by Lijian Zhao · 6 years ago
  35. 91c8e23 soc/intel/cannonlake: Add VT-d and VMX programming by Lijian Zhao · 6 years ago
  36. f1b1d92 intel/fsp: Update cannonlake fsp header by Lijian Zhao · 7 years ago
  37. e8e4329 soc/intel/cannonlake: Save DIMM information for SMBIOS Table type 17 by Subrata Banik · 7 years ago
  38. 1428f01 soc/intel/cannonlake: enable pch link in bootblock by Caveh Jalali · 7 years ago
  39. 9b50a57 soc/intel/cannonlake: Program DMI PCR settings by Lijian Zhao · 7 years ago
  40. 22d20d6 soc/intel/cannonlake: Tell FSPM UART port number by Lijian Zhao · 7 years ago
  41. e7a1e7d soc/intel/cannonlake: Fix HECI error on reset by Lijian Zhao · 7 years ago
  42. c672043 soc/intel/cannonlake: Set platform Debug Probe Type by Lijian Zhao · 7 years ago
  43. ed3e6b8 soc/intel/cannonlake: Disable CPU ratio override by Lijian Zhao · 7 years ago
  44. 84c4987 soc/intel/cannonlake: Set IGD stolen memory size to 64MB by Subrata Banik · 7 years ago
  45. c8c741d soc/intel/cannonlake: Define Max PCIE Root Ports by Pratik Prajapati · 7 years ago
  46. 2678cd6 soc/intel/cannonlake: Add PrmrrSize and C6DRAM config by Subrata Banik · 7 years ago
  47. 9027e1b soc/intel/cannonlake: Init UPD params based on config by Pratik Prajapati · 7 years ago
  48. b3dfcb8 soc/intel/cannonlake: Enable common PMC code for CNL by Lijian Zhao · 7 years ago
  49. 8465a81 soc/intel/cannonlake: Add postcar stage support by Lijian Zhao · 7 years ago
  50. b4560cd Update files with no newline at the end by Martin Roth · 7 years ago
  51. 80358a1 Revert "soc/intel/cannonlake: Add postcar stage support" by Martin Roth · 7 years ago
  52. 399c022 soc/intel/cannonlake: Add postcar stage support by Lijian Zhao · 7 years ago
  53. 0ade313 soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit by Lijian Zhao · 7 years ago